Hello All, I am trying to design a simple NAND gate using shared diffusion. I designed the IC but it is not working as expected and I don't know why. If the diffusion regions are far apart then the circuit is working fine. But I want to share the diffusion for eliminating extra diffusion capacitance and to reduce the delay. Any help will be appreciated.
I am using C5N technology and I have attached my design as zip and the schematic.
Hello dear Satvir Singh
I don't have an idea what causes your problem, but I want to mention that you don't need to make the substrate contact on the right with the p+ region (butted to the drain diffusion of the nMOS close to the output).
I cannot imagine how that can cause a problem like the one you mentioned, but I suggest that you remove the p-substrate contact (with p+ substrate tub ) on the right and test your circuit again.
Best regards...
Ali Zeki Thankyou for the reply, but I didn't understand what you mentioned to change in the design. Are you saying to remove the extra body terminals from the nmos and pmos in glade?
I have attached the photo. If this is what you imply, then still it is not working.
Dear Satvir Singh
I had mentioned only the one at the bottom on the right, which was not required.
I had already mentioned that I cannot imagine how that might cause a problem (and apparently it is not the source of the problem, as revealed by your last test).
I don't see any other problems in the design.
Nevertheless, I want to be sure about something:
What is it that problem that you say "not working" when you make the shared diffusion narrow? Is it a delay problem (e.g. The delay is not reduced as you expect) or is it a functional problem (e.g. The gate does not function as a normal CMOS NAND gate)?
Best regards...
Dear Satvir Singh ,
I see that your lay out design is logically okay where you have two pmos transistors in parallel and two n mos transistors in series.
As a matter of advice in case of logic design, one uses always the minimum area transistors. I do not think that you stick on the minimum area rule. The width or your diffusion wires are larger than 2 lambda.
In order to understand you you have to show us the two designs the working design and the nonworking design.
Best wishes
Dear Satvir Singh , I second the answer cited by Dr. Abdelhalim abdelnaby Zekry !
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