I am trying to extract series resistance (Rsd) of MOSFETs based on FDSOI/Bulk Technology, size range of these devices are 22nm/28nm to 40nm/100 nm respective of the technologies mentioned above. I am following these research articles:
1)Article A New Method for Series Resistance Extraction of Nanometer MOSFETs
2) https://ieeexplore.ieee.org/document/4509332
These articles follow similar method for finding total resistance, even though they don't explicitly say how they figured it out. From my understanding (I might be wrong!), I chose single Id-Vg curve for Vds=~0.1 V and find Rtotal= Vds/different Id (for a specific range say when Vg>>Vth). Is this the correct approach?
I also have electrical characterization data at different temperature (Cryo to Room Temperature). My ultimate goal is to have a plot showing Rsd Vs Temperature for different technologies. With Article 1 and 2, I am getting increasing trend from low to high temperature for different sizes of Bulk devices. But for FDSOI, following article 1 is giving me mixed trend whereas with article 2, I am getting an increasing trend as well. I am not sure what to make of these trends. Basically, at low/cryo temperatures, mobility should increase, that could explain decreasing trend in resistance but there could be carrier freeze out which could increase Rsd at low temperature. There's a reference for bulk tech here (Chakraborty, W. et. al. “An Empirically Validated Virtual Source FET Model for Deeply Scaled Cool CMOS”, accepted in IEDM 2019) where they show increasing Rsd trend.
If anyone could help me out that would be great. Also, If someone could explain the method of Rsd extraction based on the papers/any other resources that could be helpful as well.
Dear Fahad Al Mamun ,
I can't give the exact answer to your query but RDS is actually calculated as shown:
RDS is the drain to source resistance which is a hindrance to the flow of charge carriers from the source to drain(VDS/IDS) when the device is in ON state(VGS>VTh).
RDS=VDS/IDS at a particular VGS>VTh
Maybe this paper can help you! It takes into account things such as channel length modulation when drain voltage changes. They do a pretty good job explaining it!
best of luck!
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.baztech-article-BPS2-0011-0056/c/httpwww_itl_waw_plczasopismajtit20003-443.pdf
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