Dear Hemant,

welcome!

You circuit do not work as an AND gate. It works as an adder and multiply by one half.

So, Y= [X1+X2}]/2,

In order to work as an AND gate it must perform a multiplying function. X1 X2.

You can also process the output waveform to get the AND gate output.

You need to make a DC shift by -0.5 volt and clipp the negative part.

Best wishes

Generally in the design of any circuit logic implementation is most important.

Here you can design verilog file of memristor and creating modelfile of sub circuit.

https://ieeexplore.ieee.org/document/7939571.

To compound what Sundara has said above:

In order to design in Cadence using memristive devices you will need a memristive device model to begin with. You can find one possible model here:

Article A Data-Driven Verilog-A ReRAM Model

The equations of the model can be translated into a custom verilog component (subcircuit) that can then be used in your schematics just like any other.

After specifying the Memristor model, you can define a component using VerilogA, then attribute a symbol to your component. At last, insert the symbol to your schematic for simulation.

@Nima Shahpari... I have done all these things...after that i carried out simulation

Hemant Kumar Add CMOS buffer to the output. Sometimes, memristor causes signal degradation and a buffer can be used to restore the signal.

@Rajanish Kamat sir, i have designed the sane circuit, check please but the output is not proper.

Hemant Kumar did you find any solution ?