First, you need to cheeck that your model uses blocks that are supported by the HDL coder. In a median filter a division need to be performed and that is a complicated operation to perform in hardware. I assume that if you want to dump that design on a FPGA you are using fixed point representation and that the processing that you are performing on the image is not saturating that image. Remember that amoung the most popular format for image processing are uint8 and uint16, which are fixed point representations. I recommend that you check on those issues.