I have used a grounded MIM capacitor at output load, so please tell how to do connection for it in Virtuoso Layout XL. For eg. when I connected a simple capacitor with vdd and ground and drawn the layout as shown , there was no DRC errors but LVS error was showing pin mismatch, so please tell the procedure and send the link if any for this procedure.
http://tinypic.com/r/15i7w8y/5
From the layout it does not appear that you have connected the capacitor to ground.
The MIM capacitor is made with higher metal layers, so if you want to connect to metal1 you need several vias to reach the lower metal.
I dont remember the metal layers used in MIMC but you cannot reach them directly with metal1.
sim
yes MIM capacitor is made of different metal layers, as shown in fig. in above link, outer layer isMetal 2
middle layer is Cap Metal
inner layer is Metal 3
and innermost small squares are Via 2. this is the layout of MIM Capacitor which comes automatically when we generate from source i.e schematic.
So, what does these layer mean physically and why so many small vias inside it?
And how to connect Vdd and ground as shown in schemqtic for layout with vias?
You must reach the capacitor with metal2 and metal3 layers. Then connect the metal layers of Vdd and Gnd to these layers with contacts.
The vias are realized with small parallel vias instead of a bigger one because of skin effect. At high frequency the conducting volume is greater with many vias in parallel.
While running LVS , it is giving error "Unbound Pin", under Pins Mismatch Tool.
Why it is so.
You must put labelled pins (small square of metal) in the layout too.
Assuming basic competence, the most common problem is not knowing which of the physical capacitor plates is represented by the two plates in the symbol.
If this is not the cause, we would need to know the process you are using (= base process and number of metal layers) and to be able to see pairs of layers separately (e.g. metal1 and via1, metal 2 and via2 etc), as we can't tell what layers are present from the drawing as presented.
Assuming basic competence, the most common problem is not knowing which of the physical capacitor plates is represented by the two plates in the symbol.
If this is not the cause, we would need to know the process you are using (= base process and number of metal layers) and to be able to see pairs of layers separately (e.g. metal1 and via1, metal 2 and via2 etc), as we can't tell what layers are present from the drawing as presented.
Assuming basic competence, the most common problem is not knowing which of the physical capacitor plates is represented by the two plates in the symbol.
If this is not the cause, we would need to know the process you are using (= base process and number of metal layers) and to be able to see pairs of layers separately (e.g. metal1 and via1, metal 2 and via2 etc), as we can't tell what layers are present from the drawing as presented.
I faced similar kind of issues while connecting MOM cap. So this might help you. I presume you are not manually creating MIM rather you are generating it from the pcell of the foundry.
1>First of all, refer to particular foundry manual. In their manual, they are clearly mentioning, which metal layer must be used for respective terminals. If you are using metal layers other than those specified then LVS will not be able to detect your MIM and hence it gives error such as unbounded devices.
2> In the figure which you attached, I can't see any labeling for your MIM. So without that again LVS will lead to error.
3> After generating from the source in Layout XL, don't run any metal layers over the surface of MIM cap or make sure that MIM is totally isolated otherwise LVS will not be able to identify the device again. In your figure, your Psub is attached to MIM cap, try to avoid these kind of boundary crossings.
Though I am posting it very much lately but this might help you.
Regards,
Vinay Rao.
which metal layer should used to connect MIM capactor to MIM capacitor
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