Usually choice of sampling time is process dependent. But how to choose sampling time for a general control system problem? Is there any specific guideline? What if there is some computational delay?
1. According to Shannon's rule the frequency of sampling (f.s) of a real-time band-limited signal should be at least twice that of the highest frequency component (f.max) of the signal: f.s >= 2*f.max.
2. Continous and discrete PID controllers will have the same behaviour as long as t.s / T.i
1) Specify your target closed loop bandwidth Wb
2) Choose the sampling frequency Wc = N * Wb where N > 20 (typic. 25 is fine)
Nyquist/Shannon freq. is in general not fine since in sampled data systems the zero-order-hold generates a time delay equal to T/2 (where T is the sampling period).
Assuming to make a classical analog controller synthesis, by using the Nyquist/Shannon freq. 2*Wb, at the open loop cut frequency such a delay generates a phase lag of -90 deg which would kill any useful phase margin thus leading to poor closed loop performance (or even instability).
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