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In asynchronous design throughput is the number of data items processed by the circuit in a sec(inverse of cycle time). when ps0 pipelining circuit is designed, to identify the validity of the input signal, a control signal with input rate is used to control the first stage. so now the data items at the output side are coming with the same rate of control signal. my doubt is how to calculate the throughput with this results?
When you have a pipe line of processing circuits, every circuit has its specific processing speed measured in bits per second even if the circuits are fed in a sequence of data or vectors of bits. Since the circuits are connected in tandem the slowest one determiners the speed of whole system. In this case every circuit receives its input input bit s and write them in a register and then read them, process them and store them in an output register. deliver After which it delivers them to the input register of the following circuit which repeats the steps mentioned previously.
wish you success
Hello,
if it is not feasible to calculate delay times, you may try some trick:
Performing the above steps should result in some value for the frequency limit. Which is equal to the maximum 'throughput' your design can achieve.
Regards
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thank u sir, i tried the same thing and got the expected throughput for ps0 pipelining.
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