1.In this paper RPR-reduced precision replica redundancy compensation circuit is designed in order to correct the MDSP multiplier output. When there is wrong output beyond some threshold voltage, it is detecting the error by selecting the RPR output but how it is correcting the value. If it gives RPR output then we can know there is an error but how it is correcting. In paper it is given that it makes correction.

2. In this paper it is given that when voltage overscaling (VOS) technique is applied in MDSP block soft errors occur. How to apply that technique in xilinx tool or how to give critical path delay which is greater than sampling period under VOS to observe MDSP output variations in tool.

3. This RPR technique is to reduce the power. When multiplier output is wrong, in order to detect and correct the output we need to desing RPR, comperators, multiplexer as in proposed paper. For this we need to design basic multiplier and extra compensator circuits. This seems to be extra logics and gates and theoretically it is looking like area increasing, if area or gates increase there is chance of delay increment. But in paper it is given that area will reduce. How area reduce please explain this logic theoretically.

What is the use of this extra Reduced precision replica redundancy (RPR) technique along with multiplier. What are all applications where this technology is being applied ?