Dear colleague

Think this paper will be useful for you

http://engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf

Regards 

Dear colleague

Think this paper will be useful for you

http://engineeringletters.com/issues_v14/issue_1/EL_14_1_15.pdf

Regards 

Dear Saeed Al Rashid,

Professor, Me too having the same paper.

Anyway Thankyou so much.

Thank you for the recommendation to answer the question but i regret to say that I am not an expert in this field. Thanks!

Layman terms Naveen , that is one of my weakness (I struggle !!) will try with one of my favorite examples :

Take a (2 input- A,B , one output,Y) NAND gate testing:  Given the truth table

A  B  Y

0   0  1   

In moving VLSI industry towards IoT, requirements to BIST (Built-In-Self-Test) power consumption get exacerbated – multiple CMOS logic transistors allowing generating test vectors are responsible for near 80% of the consumed power.  According to

http://ieeexplore.ieee.org/abstract/document/4216566/?reload=true ,

Test Pattern Generation (TPG; “the reordering algorithm”) is based on read only memory (ROM) which is designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG

(the prior to “the reordering algorithm” advancement made several years ago

http://www.ijireeice.com/upload/2015/april-15/IJIREEICE%2029.pdf ).

The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns can also be stored in the same order to reduce the test power in circuit under test (CUT). Experimental results show that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG.

Dear Dr. Naveen Balaji Gowthaman,

Power is dependent on signals' switching activities. Reversing order may reduce power due to lesser switching activities. Using Hamming codes as test sequences are a viable option to save Power.