Your gate dielectric should be a good insulator, non porous, and must be a stable dielectric material.  When you measure you C-V characteristics, you should see a stable accumulation capacitance.  Try to measure the G-V charateristics also.

In order to understand such measurement try to make a good Si/SiO2 structure.

Remove the oxide layer by light etching on the back side of silicon.  Put some good ohmic contacts, and try to measure the C-V characteristics, as explained in the book Semiconductor devices by S. M. Sze.

You must learn how to put good ohmic contacts to your sample.

K. Sreenivas

Dear Sara Bazhair

in your device, you need to have as high as possible the electrical field applies/influences to the top device channel ( suppose to use the same applied gate voltage).

And to have this high electrical field (at certain gate voltage), then the used dielectric layer should be as thin as possible. Thinner dielectric, also mean smaller capacitance.

The thickness of the used dielectric is mainly determined by its quality as mentioned above by K. Sreenivas.

Hope it help

Hien

Dear Sir,

- The FET transistor is a charge controlled device. This mean, the conductivity of the channel of the FET is more or less proportional to the charge on the gate (and the negative thereof in the channel.)

- If you now want the gate to operate at low voltage, and still want a certain (high) charge in the channel, you need a thin dielectric for the gate, preferrably with high dielectric strength. This allows you to use considerable voltage on the gate.

- Until a few years back, SiO2 was used for gate dielectric. There has been a move to dielectrics with higher permittivity, because the thickness of the SiO2 was becoming so thin, that it did not work out well any more. (electron tunneling - problems with a dielectric layer only a few layers of atoms thick.)

Best Regards

Henri

thank you all,

So i should aim for a thin dielectric to achieve small capacitance and to allow the gate field to pass throught effectively to the top contacts.

but how thin is thin? and is there anny limit or range i could stick to ? 

In case i was using organic dielectric materials,

what are the best known materials for this?

what are some simple methods that could help me obtain a pore less thin organic dielectric layer?

Dear Sara,

welcome,

You want to decrease the dielectric layer thickness to achieve higher capacitance an consequently higher field effect. It is so that the the field effect charge Q= Cgs Vgs,

To work the transistor at relatively low Vgs and achieve high Q and consequently high drain current, one has to increase Cgs.

Cgs itself is equal to insulator layer capacitance, which may be a silicon oxide layer.

Then Cox= epsilon area/tox , where area is the area of the gate electrode, epsilon is the dielectric constant and tox is the oxide layer thickness. So, one has to decrease tox to increase Cox. There is a limit for the smallest tox which is the breakdown of the oxide layer. One of the major properties of the organic FETS is required high Vgs voltage to achieve an appreciable drain current Id. Vgs is of the order of few tens of a volt. Considering silicon oxide with breakdown field Ebd of about 1x10^7V/cm, then the minimum thickness tox min greater   Vgsmax/ Ebd= few 10/ 10^7= few 0.01 micrometer say the few= 6, then tox greater than 60 nanometer.

For more information please follow the link:http://www.me.phy.cam.ac.uk/publications/sirringhaus_adv_mat_2005.pdf

Best wishes

Hi Sara,

I hope you find substantial help from many kind colleagues already.

For your case, I do not think you have opportunity to research and use other dielectrics, thus SiO2 is most practical use. And My other advice to you is that: use thin SiO2 ( around 60-100 nm), created by dried oxidation, followed by annealing in N2 enviroment, at ca. 1000 degree Celsius, for several hours to have high quality of thin SiO2 layer.

Hien