How can we do sizing input and output buffers( Wgate of input and output buffers) with a given Cload for a test-bed with input and output buffers?
As far as I know: Cload = k Cgate
So, What Can we use instead of k for CNFETs? Can we use fo4 delay rule for CNFET based inverter like MOSFET?
Should I use the formula in Jie Deng thesis for CNFET modeling (attached) or the values in parameters.lib of stanford university for capacitance(e.g. Ctot)? Which of them?