I have implemented 4-bit adders (Ripple carry and carry look ahead adder) on VHDL (Xilinx ISE design suit). How can I measure speed and power of both the designs for comparison?
HAI, First you have to synthesis your design using ISE. After synthesis you will get an estimate of combinational delay / clock frequency of the design. this result you will get in synthesis report.
After place and rout will get the exact amount of delay in the circuit
Yes as Anesesh said the critical path (delay), power consumption and area overhead will be reported after synthesizing your VHDl/Verilog code. What it means is that by synthesizing any HDL implementation the corresponding gate-level of the design is generated and then based on the library file (technology size) supported by your design you can get what you are looking for.
However, based my experience usually the old technology files are shared for free.
For power measurement you require SAIF / VCD File , .PCF file and .xml file generaed via Tool ISE, and your test bench.
then give it to map->xpoweranalyser and then calculate power.
for speed you need to do implementation with constraint file i.e. .ucf file
see synthesize and implementation reports for speed and power is measured by Xpower analyzer.
without having Ucf file and clock constraint , you cannot find exact speed of your design. Also the device you choose also matters, i.e. if it is vertex 5 it has three speed grade viz. -1,-2,-3. each increases the oscillator freq. at step of 50 MHz. so if you assign goal of speed you will get max. speed out of your design. with increasing speed grade you can achieve more.
Hope it helps (HTH)
- Badges
- Science topic
- Similar topics
- Correction