How can I design a layout of NMOS which has a forward body bias applied?

05 June 2025 1 410 Report

AS i want to scaled down the threshold voltage of CMOS inverter, For the lowest level i need to give some forward bias to the nmos. How can the layout design for the same.

Simone Orcioni

Better use the FD-SOI.

https://www.st.com/content/st_com/en/about/innovation---technology/FD-SOI.html

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