in FPGA or VLSI design, How can, identified short path problem and corrections.
Hello,
Your question is very vague, but two ways to do it are
1. Do a timing assessment and look at the shortest
2. Specify the gate placement optimization for the complex logic blocks.
Regards
read paper by Jagadees et al. " FPGA-based Acceleration of Shortest Path Computation " you will find good information
I think you mean solve rather than correct the short path problems. It is known that single source shortest path (SSSP) is a fundamental problem in graph theory. However, the existing SSSP implementations on field-programmable gate arrays (FPGAs) are incapable of processing large graphs by storing the graph and results in internal memories.
This problem is solved by parallel processing as in the paper at the link: Article An FPGA implementation for solving large Single Source Short...
Best wishes
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