i work on Turbo decoder using Fast Add Compare Select Unit.I required a vhdl or verilog code for Turbo Decoder using combination of viterbi and deinterleaver or some other methods..do you have any algorithm for Turbo Decoder VLSI implementation?
Hello, have a look here,may be you will find more https://www.researchgate.net/publication/3090864_VHDL_implementation_of_a_turbo_decoder_with_log-MAP-based_iterative_decoding
Article VHDL Implementation of a Turbo Decoder With Log-MAP-Based It...
Here you can find some codes:http://www.expertcore.org/viewtopic.php?f=8&t=866
hello
I have ever seen the best website for download sample code and project ,you can find more correct project and code with document :
http://opencores.org/projects
If you have had any problem from website please contact me.
Otherwise, if you are looking for some optimized architecture/algorithm then refer some IEEE transactions or reputed journals and try to implement it on your own.
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