This IFFT/FFT (link below) was written in VHDL (I used it for Xilinx-FPGA but without using IP-Cores or Xilinx specific components so you can also use it for Altera).
Goal was to reach a high data throughput/data rate with some limitations in computation accuracy. So a parallelized structure was used. If speed is no problem but computation accuracy more important you can use "in-place" calculations with radix-2.