You mentioned the sneak path problem in your project "Goal: Design Memristor Arrays which can overcome the sneak path problem"
Thank you, Dr. Murthy. Those linked-to items explain sneak paths perfectly.
Usual array of memories consist of one transistor and one storage element (capacitor in case of DRAM or a cross coupled latch in case of SRAM). The transistors connected to the wordlines (rows) act as switches to select the cell. The data is accessed (read or written) through the bitlines (columns). To access data from the cell (i.j) the ith wordline is activated along with the jth bitline.
The transistor switches ensure that all the other cells of the array are isolated.
The question here is can we make arrays without the transistor as a switch for each bit of data?
The goal is to make the Resistive RAM (RRAM) without the transistor switch.
The figure below is from the paper titled "A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array" (Figure 1 (a) - 2D structure of 3x3 RRAM crosspoint array)
Figure is attached.
The cell to be read is located at 1x3 position in the array (green colored).
Expected case: The potential difference across the terminals of the selected cell to be made Vread and across all other terminals to be zero. Thus, the current passing through Rsense purely depends on the resistance of the selected cell.
Actual case: The cells (HSC- Half Selected Cell) which fall on the row (red colored) and column (blue colored) experience a potential difference of Vread/2 when the potential difference between the terminals of selected cell (FSC- Full Selected Cell) is Vread. Thus, the current flowing through Rsense is contributed by both FSC and HSCs through sneak path (multiple path in array).
The read current is disturbed by the current flowing through sneak path from the HSCs - is termed as sneak path problem.
Dr. Kittur, Thank you for an even more excellent explanation! I notice that each node (cell?) in the figure shows a capacitor to ground from the bit line and from the word line (2 capacitors). Are these capacitors purpose-built MIM capacitors, or are they incidental, parasitic, 'stray' capacitances?
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