I have a new device and I have drawn the layout for it. It doesn't have an associated schematic. Would it be possible to extract the parasitic caps for it?
Yes, definitely. After all the extraction is done as a feed to the LVS, so before the LVS. But if the layout is not sensible (from LVS point of view) you may not necessarily know at what result you are looking. I have had the issue for instance when a drain area was not touching upon a gate area (used in a pad), for which my then software couldn't figure out what I 'intended' to make: no extraction rule for that device :-(. So the extracted netlist was rather non-sensical.
Yes, definitely. After all the extraction is done as a feed to the LVS, so before the LVS. But if the layout is not sensible (from LVS point of view) you may not necessarily know at what result you are looking. I have had the issue for instance when a drain area was not touching upon a gate area (used in a pad), for which my then software couldn't figure out what I 'intended' to make: no extraction rule for that device :-(. So the extracted netlist was rather non-sensical.
Actually its a new device and it's yet to be modeled at the circuit level and thus I don't have a corresponding schematic to it.
This I answer as a former designer of non-manhattan chip layout software, but that was in 1986, so 'in a previous life'. Then again I guess the principles should not have changed so here I go:
For a new device you may have to adapt the extraction rule set. Typically your existing rule set is supplied to you by the lib supplier or the fab. Depending on many variables you may be able to define your own extraction rules. Extraction works like: (poly AND active area) to get the transistor region, transition of that area to active area only = drain/source etc. Beware of exclusion layers and other layers to indicate special operations.
I am not sure you wanna go that route, but for a new device you may not have an alternative :-(. If you must go that route: do make a save set, and start playing around first with it to get acquainted. First time making extraction rules is quite challenging.
Thanks a lot Rob ! I do want to define my own extraction rules.The software isn't able to figure out what I am doing and it's throwing random errors. I will start with what you are suggesting.
Just to reiterate, I will move on to make the changes in the rules and then after DRC , I can skip LVS, since I don't have the schematic? I think the other path i can take is modelling the device at circuit level and then running LVS(of which I am sure it will give errors )
Anush..I am working on cadence virtuoso and process node is 130nm.
Nothing to add on your comment Nishtha, except that maybe you will want to develop the LVS too. I am not sure how that works for your tools, it might just be that the tools only support caps, resistors and transistors, but can't try it out for you, currently no access to any license.
Having said that, my guess would be that in extraction you will define a final device and its nodes. That means: a real string for identifier. Your definition may be split as the generic device name (e.g. newDeviceType) and the first characters for its instance (e.g. nd, giving names like nd0, nd1 etc), but that is of course tool dependent. Something alike you can arrange on schematic side, probably with a netlister switch, marking your new device as a leaf cell for the netlist graph (=stop expanding into the device). In my experience Cadence is not very good on netlists (and shame on them for that!) but the principle should hold.
So you would end up with your own defined name on lvs, same kind of cell class name on schematic side. That gives LVS all it needs to compare the graphs and find comparable leafs, so the equivalence map between the two. And then in its final stage it can compare the cells attributes (L and W for transistors as an example) and check the match. Here an extra variable pops up again, the default tolerance you want.
As for getting into LVS with own defined characters: first play again. Try for instance resistors, (extra layer required?), with a bunch of them partly parallel, partly serial.This is quite common with resistors, built as a zigzag structure, with metal connecting the resistive pieces, so you get a well defined, well repeated structure but avoid the corners in resistive material for crowding effects in the corners. The parallel and serial effects stress the LVS to its max...
Of course, LVS can be left altogether. But then for a real chip you will have to add some extras anyhow like block layer or so, to shield your new device away. Probably doing the extra step instead is really worth the while. I have once avoided doing the extra step (for that pad example), replacing the cell with a phantom cell once I was at LVS, But that was with Compass (nineties!). Their tool allowed on the ascii layout files the use of sed as automatic search and replace, so that was simple....
You may have a look at PEEC. There are PEEC tools around doing a complete extraction of L an C for younprovided you can transfer your layout to a format understood by these tools. A Simpler approach to make use of FastCap and FastHenry tools. Should be OpenSource.
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