I am working on one of the paper on clock domain crossing. I am searching relevant papers which are tested as a proof of concept on FPGA.
There are papers which talk of RTL Simulation but I am interested to look for papers which have tested their CDC design on FPGA .
In chapter 6 of book Advanced FPGA design by Steve Kilts
clock domain crossing was discussed.
In our work entitled "Using hardware parallelism for reducing power consumption in video streaming applications" We had two different clock signals with no phase shift (sourced from the same source) where we used FIFO structure to manage pixel transfers between the two clock domains
Thanks for suggesting the book.
I have gone through your paper Karim and it seems that the clock2 is always a multiple of clock1 (clk2 = clk1/2 or 4 or 8 ..)
You have taken the case where both the clocks are in phase .
I have verified my cdc for the clocks with same phase and now working on cdc for clocks with different phase .
Anyways Thanks for the help !
Clock Domain Crossing (CDC) Design & Verification
Techniques Using SystemVerilog by Cliff Cummings, Synopsys User's Group 2008: http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
http://www.edn.com/electronics-blogs/day-in-the-life-of-a-chip-designer/4435339/Synchronizer-techniques-for-multi-clock-domain-SoCs
http://www.fpgadeveloper.com/2009/09/generating-clock-domain-crossing-fifos.html
https://fpga4fun.com/CrossClockDomain.html
http://www.eetimes.com/document.asp?doc_id=1276114
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