I have fabricated TFTs on SiO2(300nm)/Si(n++) substrate using ZnO as an active layer of thickness 10nm-30nm. For all TFTs, it shows ambipolar behavior!!!. Can anyone tell me is it the problem with device structure or measurement error?
i have attached the transfer curve of ZnO TFT with different drain bias.
Inference from the graph:
1. carrier type switchs when Vds=Vgs
Note:
Structure: inverted staggered; W/L= 2000/100
ZnO: Reactive dc magnetron sputtering; S&D= Ag (thermal deposition)
Characterization: Keithley 4200 SCS
Hi there, your gate voltages are quite high (several tens of volts across 10-30 nm ZnO) . Have you considered hot carrier injection? Wim Willems
@ willems, Thanks for your reply. I didn't think about hot carrier injection in my device, i will look into that.
Can u mention some reference papers/links on this topic?
muhammed, I noticed your unanswered question, but it was in the early 90's that I worked on electrical conduction in thin films. I haven't got a contemporary reference. The Wikipedia article on hot carrier injection may be helpful.
have you checked that your gate current is low compared to you drain current, if not your device just leak
Indeed, Jingjing, which is to be expected at an electrical field strength of 10^9 V/m. Wim.
I agree with Emmanuel and Jingjing. What you measure is pure leakage through you gate insulator (i.e. your SiO2). Have you patterned your ZnO film? If not the whole "wafer" (i.e. sample) leaks because you have your gate (doped Si) everywhere. You have to either pattern your gate, or ZnO or pattern both. Then you should get proper TFT response (if ZnO is deposited properly). Can you tell me why you use Ag as your contacts? What about using aluminium?
Thanks for your reply. I didnt perform Vgs-Ig characterization, i will do that to confirm whether its leakage current or not.
@leszek A Majewski, I have patterned ZnO layer on SIO2/Si wafer, not gate. Gate contact drawn from top side of the Si wafer, after removing SiO2 by scratching with diamond cutter.
On general basis The Si/SIO2 wafer leads to a lot of leak, if you do not need large gate capacitance go for fairly thick SiO2 layer (400nm up to 1µm) leakage will be weaker
also I get better result by let the system rest after active layer deposition. This is particularly true if you make silver paste contacts, do not perform any measurement until the latter is really dried
a good FET operate in the regime where the drain current really prevaisl over gate current (factor 10 is really weak, 1000 and more is better and far more convincing for referee) at least on the on side. On the off side it is more common tobe leakage limited.
Muhammed, measure output characteristic (i.e. Isd vs Vsd) of your devices, as well. If you have a problem with leakage you will see it immediately! What are the channel length and channel width of your devices?
I agree with Leszek. Your output curves will confirm if it's leakage current (the current onset departs far from zero drain-source voltage. Output curves also tell you if the device is ambipolar.
Have you checked the conduction and valence band of your ZnO? (to see how relative it is to Ag WF, supposed your ZnO is undoped).
if you share your output and transfer characteristics of your device....it would be easy to give a good suggestion..
For your information take a look at our paper attached here
Article High-performance chemical-bath deposited CdS thin-film trans...
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