I didn't get any hysterisis in MFIS NC MOSFET .Can anyone suggest me how to get hysterisis in Id_Vg graph?
Hello Sasikala Panneerselvam
What is a 'MFIS NC MOSFET'? What does the abbreviation 'MFIS NC' mean?
A normal MOSFET just has a parabola characteristic (in strong inversion) and should not have a hysteresis at all.
If a MOSFET has a hysteresis in measurement this normally indicates some kind of charge accumulation in the gate oxide. This is something I would regard as undesired and alarming rather than intentional (except it is a floating gate device for a non volatile memory).
( Metal Ferroelectric-Insulator-Semiconductor (MFIS) its a structure type. ie) ferroelectric is in direct contact with the oxide layer. NC means Negative Capacitance .It is a FERROELECTRIC-BASED negative capacitance (NC) MOSFET.
Hm,
sounds like a memory device that should have an intentional hysteresis.
For SPICE like simulators this is a problem because in SPICE the model usually is in the simulator code. To simulate that kind of thing you have to compile a special version of the simulator itself.
Some SPICE versions support behavioral models but then things become somewhat simulator version specific.
For SPECTRE things are different: You can write a verilogA model. In the verilogA model you can write whatever you like. If the model doesn't show the expected behavior you have to change the verilogA until it works. (Careful: SPECTRE has a SPICE-compatibility mode. If you describe the device in SPICE style it runs built in SPICE models)
Which simulator do you use?
Did the simulator really make a sweep up and a sweep down (some simulators always sweep the same direction in DC simulations)?
In some cases it helps to run a transient simu with a ramp up and a ramp down at the gate and then post process the data to convert Ids(t) and Vgs(t) into Ids(t) versus Vgs(t).
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