During in-situ conductance measurements, the gate potential was varied from -0.8 V to 0.6 V (anodic cycle) and reverse measurements from 0.6 V to -0.8 V (cathodic cycle). I have observed a huge difference in the conductance vs gate potential plot for the two cycles. conductance remain high even at more negative potenital for cathodic cycle compared to anodic one.
These measurements were done for PEDOT-PSS coated on gold IDEs (5 um spacing).
Can anyone explain the possible reason for this?
I have attached the plot along with.
Thanks,
Rekha
Here is the potentiodynamic curve associated with the above measurements.
observation of hysteresis may be associated with relaxation phenomena at the interface. if so, you may get reduced hysteresis with slow potential scanning. you may try to carry out the experiment at very slow potential scan rate, e.g., 1 mV/s.
- Badges
- Science topic
- Similar topics
- Chemistry
- Electrochemistry