It would take schema - little information.

If the transistors are MOSFET, I can think of a current mirror decoupled in AC with a series resistance. I think you can find it in many LNA papers.

S.

Respected Josef Punčochář ,

I have mentioned my schematic what I am using, i.e., Inductively degenerated CS topology.

You must search all available biasing circuit such as voltage reference and current reference or even resistive divider and you can compare it by analyze noise figure of the whole schematic but it might be very difficult if you use complex voltage reference. The other way is simulate noise figure with SPICE based software such as Cadence Spectre or Agilent EESoft which is more expensive

.

Vasudev:

.

You have only asked half the question: the other half is

"What specific functionality are you aiming to achieve

by your choice of biasing?" This will set the zero-signal

operating current of the active device (is that a BJT or

MOS transistor?) to meet a mixture of objectives. Note

that these are mainly zero-signal criteria; the presence

of large input signals will - as matter of necessity - alter

the bias conditions dynamically and deeply. Depending

on the magnitude of these "blockers" (as they are often

identified) the overall power gain of the LNA will change

on a cycle-by-cycle basis, thus causing intermodulation

of the "wanted" carrier, leading to many side effects; the

chief of which are the generation of spurious harmonics 

(known as "spurs"), and time-varying modulation noise

in the output spectrum, Further performance errors are

introduced by the modulation of the input match, as

the instantaneous working point of the active device

is pushed around by the blocker.

 .

But back to the choice of the zero-signal (essentially the

same as the small-signal) bias point.

.

First, the bias current (and the associated voltage at the

collector/drain node) will determine the nominal fT of the

transistor, upon which we depend to convert the emitter/

source branch inductance to a nominally purely-resistive

input impedance at the base/gate input node of the LNA.

.

The key word 'nominally' is used in all these comments

to make it clear that every single variable in the design of

real - as opposed to theoretical - circuits is susceptible to

large variations from its nominal 'modeling' value, These

variations arise in the manufacture of all components in

the circuit, as well as being induced variations caused

by the signal itself. This fact renders elaborate equations

often used to 'analyse' circuit behaviour all-but useless in

the real world of design.

.

Second, the bias current will determine the overall power

gain of the LNA, This is one of several key considerations

in the design, and may permissibly vary over a few dBs.

The power gain (and associated matching criteria) often

needs to be held as close as possible to its nominal value

over wide variations in operating temperature, the extent

of which depends entirely on the application of the product.

.

Thirdly, it will determine the the nominal noise figure of an

LNA. Here, one must be careful, in practice, not to degrade

this variable by poorly-conceived biasing arrangements. It's

also important to keep in mind that the overall noise figure

of a receiver will always be considerably worsened by the

noise introduced by later stages, notably by the mixer(s).

.

There are other factors to be considered in forging a highly-

optimized LNA for a particular application. Biasing accuracy

is important, and there are many ways the required circuitry

can be designed. But only when all the essential desiderata 

have been considered, and the necessary trade-offs have

been made can one turn to the details of biasing.

.

The point to be made here is that you need to be quite sure

of your performance objectives before "worrying" about how

your circuits are to be biased. Don't misunderstand the point:

biasing is a very important aspect of good design practice.

Sometimes, it actually is the starting point of a certain design.

Only when the OVERALL OBJECTIVE of a design has been 

FIRMLY ESTABLISHED can this determination be made.

.

Barrie

@ Barrie Gilbert

Respected Sir

Thank you very much for your valuable points.

Actually I am targeting to achieve high gain,low power and moderate NF and aiming to keep  all these parameters  constant (@frequency of interest) under  different corners and temperature.

I have one more doubt in mind, what is the maximum range of gate  inductor in IDCS LNA , which is feasible on IC's?

Vasudev

Vasudev:

.

I rather sounds like you are looking for someone to design your

LNA for you. If such is the case, there will be a very large number

of details that would need to be conveyed, including the specific

gain you wish to achieve, between what source impedance and

what load impedance; at what frequency; using what process

technology

.

Note: The above answer was - somehow - greatly truncated.

But I think you will see the point I am striving to make, here.

.

Barrie