For the read operation, the WL will be at logic high (Vdd or let 1V) and initial condition at internal nodes (let Q and QB) are 0 and 1 V. The BL and BLB are also precharged to logic high.
However, in the write operation, BL=1V, BLB=0V, Q= 0V & QB=1V, and WL are logic high for the operation to be started.
I just want to know whether these inputs (BL, BLB, and WL) are pulse or simply provide the DC supply. If possible provide signal details for read and write operation for better understanding or any hspice netlist.
WL is pulse and raise when Read or Write operation is to be performed. For a conventional 6T SRAM, WL normally remains low; thus, isolating the storage nodes Q and QB from BL and BLB. Whenever a Read or Write operation is to be performed, WL is raised to high. The pulse width of WL is governed by the time required to complete the Read/Write operation. BL and BLB are normally clamped to Vdd (may differ for a different architecture) and remains charged. It is rendered floating during Read operation by raising/disabling the Precharge circuit/signal. During Write operation, Write Driver places appropriate value of BL and BLB. For more details and clarity, you shall read
Analysis and Design of Digital Integrated Circuits (McGraw-Hill Series in Electrical Engineering) by Hodges, Jackson and Saleh
http://www.engineering-bachelors-degree.com/electronic-components/uncategorized/sramreadwrite-operation/
Dimitri@Thanks a lot for letting me understand the concept with your help.
You may find this chapter on Semiconductor Memory Design useful. This is Chapter-8 from David Hodges' book.
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