when I'm finding output of first stage of the circuit it is giving correctly but as I'm using this output as input for the next stage...it is deteriorating... I'm using proper clock zones also...can anybody help me out in this ?
Dear Rupali,
If you have a multistage circuit then it is understandable that you test every stage separately and verify that their operation is correct.
After that you when connecting the stages with each other one has to consider the loading of the trailing stage to the previous one. To overcome the problem of loading one uses buffers and drivers.
The other issue is that you have to make precise timing of the whole system such that the stages must be correctly timed in the sense that the output from the previous stage falls with clock edges of the trailing stage.
It is a good practice that one integrates the system stage by stage till one integrates them all.
If you have multirate stages, then you can use registers at the input and output of the building block to input and output the data to and from the circuit.
These are some conceptual guidelines hoping to help you.
wish you success
Can you provide me details on how to correctly design a circuit using clock zones? I'm facing problems in deciding the clock zones for a layout. Eager to hear from you.
QCADesigner is a good software but has big bugs. probably you see one of these. in the large circuits have strange bugs.
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