I've been trying to make a discrete-time integrator same as what's given in Razavi book, chapter 12(switched capacitor). I should design it at transistor level, not Macromodel. It doesn't integrate, and I can't find out what is wrong. I just tried all possible biasing that I can think of for switches. For opamp, I used both simple differential pair, and a folded cascade, none of them gives integration.

.SUBCKT opamp Vb inp inn outp VDD

M0 n Vb 0 0 CMOSN L=2u W=20u

M1 outn inp n n CMOSN L=0.2u W=2u

M2 outp inn n n CMOSN L=0.2u W=2u

M3 outn outn VDD VDD CMOSP L=0.2u W=4u

M4 outp outn VDD VDD CMOSP L=0.2u W=4u

.ENDS

X1 Vb inp inn Vop VDD opamp

M1 Vin ph1 n1 n1 CMOSN L=0.2u W=1u

M2 n1 ph2 0 0 CMOSN L=0.2u W=1u

M3 n2 ph1 0 0 CMOSN L=0.2u W=1u

M4 n2 ph2 inn inn CMOSN L=0.2u W=1u

C1 n2 n1 50f

C2 inn Vop 50f

V0 VDD 0 1.8

V1 Vb 0 0.6

V2 inp 0 0.9

V3 Vin 0 pulse(1 1.5 0 5p 5p 500u 1m)

V4 ph1 0 PULSE(0 2 0 5p 5p 80u 200u)

V5 ph2 0 PULSE(0 2 100u 5p 5p 80u 200u)

Please have a look at attachments. N1 is node connecting to one end of capacitor C1, INN is the negative input of opamp (C2). I give the results for 2 values for capacitors:

C1=50 fF , C2 = 50 fF

and

C1=50 fF , C2 = 1 pF

I think opamp never turns on, cause it's just VDD at the output.