The signals attached in this file

Could you please explain the waveform ?

The first signal is gate voltage of the PMOS varies from 25 V to 20 V

Current in the source of the PMOS, current in the gate of PMOS, the drain current of the PMOS, the inductor current, the switching node voltage, the same curents for the NMOS, drain,source, and gate, finally the voltage of the gate NMOS

This is a Miller plateau in power MOSFETs due to the Cgd discharge.

Good links explaining this phenomenon:

http://electronics.stackexchange.com/questions/66660/why-is-the-gate-charge-curve-miller-plateau-of-mosfets-dependent-on-vds

http://www.ti.com/lit/ml/slup169/slup169.pdf

Yes, when the switch is turning on or off, the voltage changes rapidly, and that dv/dt induces a current to the parasitic capacitors (equal to the dv/dt times the parasitic capacitance) of the transistor, in the case of the miller capacitance, which is connected to the gate, this current is drained from (or to) the gate (depending if it is turning on or off), causing this kind of effects.

May be your question is how to avoid or at least reduce that effect, you may increase the gate resistance (add a gate resistance of some ohms in the gate if it doesn´t have) to reduce the dv/dt but this would reduce the of the transistor increasing the switching losses, that is a constrain, you can also add a small capacitor from the gate to the source (in this case reduce the gate resistance to match the speed you want), then the current throw the miller capacitance would cause a smaller voltage increment in the transistor gate.

In other topics, check if there is any cross coupling, that means the gate voltage increases after the dead time, due the switching of the other transistor, in this case you may change to a symmetric voltage gate drive, that means you turn off the transistor with –V instead of cero, this prevents the voltage to increase over the threshold voltage.