This is related to the bandwidth of the controllers and the synthesis capability of the PWM.
For PWM applications, we typically have a fixed switching/sampling frequency. Thus, in order for the PWM to adequately synthesize the current controller output, the current controller’s bandwidth is often limited to 1/10 of the switching/sampling frequency.
For the same reason as before, in order for the current controller correctly follow the current reference generated from the voltage controller, the voltage controller should have a bandwidth lower than the current controller (often considered 1/10).
You may find additional and more detailed information in digital control books.
It is not correct to identify "voltage" and "current" control as faster and slower, respectively.
The commonly used approach in any multi-loop controller design is that the innermost loop should have the fastest response. The bandwidth of the controllers should progressively decrease towards the outer loops. This helps to design the controllers in each loop independently.
For example, there are three control loops, and you are designing the controller for the middle loop. To design the controller independently, it is required that the input from its outer loop should have lesser bandwidth (varies much slowly) and behaves like a good reference signal. Similarly, it is not hard to see that the variation in the output of this loop (input to the inner loop) should be much slower than the inner loop dynamics, and therefore behaves like a good reference input. This necessitates the second loop bandwidth to be much slower than the inner loop bandwidth and much faster than the bandwidth of the outer layer.
On a different note, the choice of currents and voltages being the inner and outer loop control variables is due to the nature of the dynamical equations of these systems.