I have seen in almost all processor, L2 cache associativity is some power of 2 (L1 is generally direct mapped or some low power of 2). Although in Alpha 21164 super-scalar processor L2 cache (96KB) was 3-way set associative. Which doctrine had convinced the architect of alpha 21164 processor to not to have the associativity some power of 2 ?
Assuming a uniform distribution of addresses, evenly distributing references across cache banks requires dividing the address by the level of associativity. This is much easier if that is a power of two. Also, the cache banks usually fit into a more rectangular area when you have power of 2 associativity.
Some processor designers have decided that a preferred cache size (3 banks, usually) is preferable to maintaining those properties.
If you refer to any book on Computer Organization, you will find how the address from the CPU can be partitioned for implementing an associative cache. Having the number of sets to be a power of 2 makes it convenient to implement the cache.
The final design decision is a trade-off between power, speed, etc. As a result, it might be beneficial to sacrifice the power-of-two symmetry in order to allow an overall more balanced design.
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