In semiconductors one effect is that specially when exposed to the neutron radiation the trap are created which lead to decrease in the mobility so the current also decreases.
The radiation also creates traps in the oxide (SiO2) which can lead to the shift in the threshold voltage
As it is, a PMOS transistor with a give RDS and operating voltage is three times as large as the equivalent NMOS transistor. Given a constant area of influence of some radiation "event", the percentile of area affected of the NMOS is thus 3 times that of the PMOS. Hence the difference.
I would like to elaborate on the answers of Kakkar and Dreher for those to whom the implications of the technical arguments are not obvious.
PMOS transistors, due to the use of holes rather than electrons as carriers, are slower and carry less current. As a result of the latter they must be two to three times larger to balance with paired NMOS transistors.
For small radiation events *only*, the PMOS are simply larger and slower and contain more charge and are therefore harder to upset. For large area radiation events, it really makes no difference, either is swamped.
One might think you could gain some advantage by using more PMOS, but it is inefficient and slow by orders of magnitude. Even just making everything larger is inefficient compared to redundancy techniques. I have numerous technical papers on redundancy schemes if someone needs a reference. The latest is linked below.
Article Configuration Tests of RHBD Library with DICE, TAG4, Dual Ra...
I wouldn't say it is a general rule. It depends in the technology process, circuit under study, the kind of radiation specie and the effect you are considering. Regarding total ionizing dose (TID) what is generally accepted is that charge trapped in MOS oxide will shift negativelly the threshold volgate in NMOS leading to unacceptable drain-source leakage current. In PMOS the opposite occurs, increasing threshold and reducing leakage. You can check Ma and Dressendorfer book for better understanding this phenomena. Regarding transient faults, as mentioned above, in CMOS implementation given same current transistors, the associated capacitance for NMOS will be lower than the one for the PMOS. Is not true that NMOS current is three times PMOS current for same size transistor. In modern processes short channel effects as saturation velocity reduces this ratio to a much lower value. In this context, you can say that an isolated NMOS will be more vulnerable than PMOS. As this situation is not very common in circuits, what matters is the specific capacitance associated to the node under analisys, the collection area that will charge this node, and the transistors (NMOS or PMOS) that will fight against charge build-up and the change in voltage node.
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