Hello
I have few quires about modelling NBTI Trapping/Detrapping Model Based on Predictive Technology Model (PTMs) firstly for CMOS and then FinFETs for smaller tech. nodes such as 16nm/22nm/32nm/45nm.
Q1: What material PTM (CMOS and FinFETs) models used for Gate-Oxide (e.g. Aluminium oxide Al₂O₃ or Hafnium oxide HfO₂ etc...)?
Q2: Based on above material, what is the typical trap density (i.e. number of traps/cm^2) for 16nm/22nm/32nm/45nm PTMs?
Q3: What is the typical Activation Energy (Ea) value for trapped charge emission? and what is its' range?
Thank you.
Usman
http://ptm.asu.edu/
Dear Usman,
This question attracted me to carefully read it. I think the best people who can answer your question are the founder of the Predictive Technology models.
However interface state description and modelling is not a new topic. It started intensively with the advent the MOS and the MIS devices and transistors. The best studies made on the interface state and their effect on the material and device performance were made with the start of the MOS technology. The field effect could be demonstrated first when the interface states between the silicon and silicon dioxide are technologically controlled. The story of the interface states and their understanding and control is an appreciable part of the success story of the surface field effect devices.
So, to predict the scaling effect on the interface state in the field effect devices you have to follow the performance of the MOS and MIS capacitor and the their control on the FET transistor among the different MOS generations. Prediction is an extrapolation process based on the tendency of performance with time and the basic physical laws. So, one can discover the properties of the next node before it is realized in experiment.
The interface states themselves are due to unsaturated dangling bonds at the surface of the material.
They can act as traps of a type of charge and also they can act a scattering centers impeding the motion of mobile charges and also they can act as recombination centers for the minority carriers.
Interface states are reduced by a process called passivization such that their effect is has little or acceptable effect on the device performance.
Yes this is not a direct answer on your question but may be helpful to consider some concepts and principles relating to it.
wish you success.
I saw in literature that latest CMOS and FinFET (smaller technology nodes) technology is mostly based on Hafnium oxide HfO₂; whereas various research groups are using different structures of Hafnium oxide HfO₂.
Anyways, I was wondering if someone can refer me to the BTI paper where we have stress time starts before around 1n sec (i.e. 10^-9) as clock frequency in todays' circuits is more than 1GHz.
There are many papers where they start stress time and recovery time DeltaVth graphs with 10^-3.
To my knowledge there are not many exp. data below 1 us recovery time. People always try to extrapolate their data into the relevant ns region. A rather old paper from Tibor Grasser (T.U. Vienna) discusses the problems associated with that quite extensively
http://www.researchgate.net/publication/4322546
I think that the main problem is, that you have to accelerate the aging by enhanced voltage and temperature, but that the recovery has a different voltage and temperature dependence than the stress aging – so you need a good model to predict long term aging and recovery at realistic use conditions.
I like the model from the Mahapatra group (IIT Bombay), IRPS 2015 paper 4A.3
DOI: 10.1109/IRPS.2015.7112725
if one can be satisfied with the mean values. If you also need statistical values you should better apply the Tibor Grasser model
https://www.researchgate.net/publication/254040577
_Recent_developments_in_understanding_the_bias_temperature_instability
We have applied this model in HSPICE Monte Carlo simulations of 16nm CMOS Flipflops and SRAMs and it works great. I upload our paper from the Synopsys user Meeting SNUG 2012 and our paper about Flipflops into researchgate so you can see them.
https://www.researchgate.net/publication/260721141
_Resilience_and_yield_of_flip-flops_in_future_CMOS_technologies_under_process_variations_and_aging
and https://www.researchgate.net/publication/280317334
_A_STATISTICAL_MOSFET_AGING_MODEL_FOR_MONTE_CARLO_
SIMULATIONS_WITH_HSPICE
Conference Paper A rigorous study of measurement techniques for negative bias...
Article Recent developments in understanding the bias temperature instability
Article Resilience and yield of flip-flops in future CMOS technologi...
Conference Paper A STATISTICAL MOSFET AGING MODEL FOR MONTE CARLO SIMULATIONS...
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