Hi all,
I would like to know if someone know the data from a white paper/report/research paper about
-> SoftErrors: Failure in Time (FIT) rate (neutron/meoun/proton etc.) for some Flip-Flops which are based on FinFET and/or FDSOI technologies. As there are few papers available on SRAM FinFET FIT rate. Furthermore, there are few papers on CMOS FIT rate for flip flops are also available.
Thanks.