Hi all,
I would like to know if someone know the data from a white paper/report/research paper about
-> SoftErrors: Failure in Time (FIT) rate (neutron/meoun/proton etc.) for some Flip-Flops which are based on FinFET and/or FDSOI technologies. As there are few papers available on SRAM FinFET FIT rate. Furthermore, there are few papers on CMOS FIT rate for flip flops are also available.
Thanks.
Hi,
I don't have direct access to any white papers on flop SEU and FIT rates but I can say that in typical designs, the FIT rate of sequential logic, at least in terms of retention cross-section (without accounting for logic or timing derating - if you want to include this, and assuming a flop has the same fail rate as SRAM, derating will reduced the actual flop error rate to 5-10% of the measured retention value in most logic designs), is about the same as that of the SRAM - in other words if you put and array of flops in a neutron beam/alpha source and an SRAM array with the same number of elements as the flop array, the failure rate will be similar. It is true that flops with higher drive transistors (wider gates) can have a reduction in failure rate but we usually see all flops from a technology library from the weakest to the strongest are about 2x higher than SRAM (in the same technology) to about 15x lower failure rate, In a FIINFET technology I would expect the same trend to be followed since the sensitive element in the SRAM and the flop is the same or similar FinFET transistor.
Sorry if this is to general for you needs, but if you are trying to design experiments, the rule of thumb above has worked for many generations of bulk and SOI devices and I assume will work for FinFET as well.
One note, I am assuming you are referring to standard flops and not DICE or some other redundant flops which, of course, would have a much, much lower failure rate.
Hi,
I don't have direct access to any white papers on flop SEU and FIT rates but I can say that in typical designs, the FIT rate of sequential logic, at least in terms of retention cross-section (without accounting for logic or timing derating - if you want to include this, and assuming a flop has the same fail rate as SRAM, derating will reduced the actual flop error rate to 5-10% of the measured retention value in most logic designs), is about the same as that of the SRAM - in other words if you put and array of flops in a neutron beam/alpha source and an SRAM array with the same number of elements as the flop array, the failure rate will be similar. It is true that flops with higher drive transistors (wider gates) can have a reduction in failure rate but we usually see all flops from a technology library from the weakest to the strongest are about 2x higher than SRAM (in the same technology) to about 15x lower failure rate, In a FIINFET technology I would expect the same trend to be followed since the sensitive element in the SRAM and the flop is the same or similar FinFET transistor.
Sorry if this is to general for you needs, but if you are trying to design experiments, the rule of thumb above has worked for many generations of bulk and SOI devices and I assume will work for FinFET as well.
One note, I am assuming you are referring to standard flops and not DICE or some other redundant flops which, of course, would have a much, much lower failure rate.
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