This is a question without a single answer, since there are many variables and dependencies here which are impossible to pin down, and will change according to design parameters, technology generation/features, logic/circuit design methodologies and capabilities, and (very importantly) the design of the memory hierarchy, and the workload(s) under consideration. Even the basic metrics (power, and performance) are subject to much discussion: how should one trade off power vs performance to make a "fair" comparison? Nonetheless, it would be interesting to hear folks' opinions and analysis on this topic. To start things off, let's assume that you need to meet a certain ("relatively high") performance level, measured as performance per thread in a multi-core/multi-threaded microprocessor, but you are also subject to a per-thread power constraint (typical of today's high-performance processors). Obviously, the deeper the pipeline, the higher the operating frequency. Or, frequency can be traded off for power, by lowering the operating voltage. However, lowering the design FO4 and deepening the pipeline will impact the power-performance of the design in a variety of ways:
1) Number of flops in the design increases, driving up power, especially power used for clocking. Also, the delay overhead of the flop and any clock uncertainty takes a relatively larger bite out of the cycle time.
2) "Design difficulty" increases since logic has to be divided more finely to achieve the higher cycle time. Also increased timing/device modeling accuracy is called for. Tighter signal slews will be required, and number of repeaters/buffers will increase.
3) CPI will increase, since miss penalties (measured in numbers of cycles) will increase. Also, in light of #2, the design may be pushed towards a simpler microarchitecture.
4) There may be many other costs, depending on the design, ranging from SER impacts, power/current density issues, cache design issues, etc.
I'll start by suggesting that, given where most commercial designs seem to be landing, that 10FO4 is probably well below the ideal cycle time (despite considerable literature which might suggest otherwise). Also, something like 50FO4 is probably too high. Comments anyone?
Tough to say. We have top-end processors running at 4GHz that are fabbed in 14/16nm. Inverter FO4 for those technologies is ~10ps. So about 20-25 INV-FO4-equivalent cells sounds right, plus some overhead from clock uncertainty, variation, etc.
Samuel Pagliarini sounds in the right ballpark... but would your intuition (or analysis) lead you to believe that your designs are near the optimal point for that technology? If you could push the FO4 down a little without too much disruption, it might argue for a lower number. Or, conversely, if you could save a lot of flops/leakage/clock power/CPI/etc. by moving towards a higher FO4, that would argue for moving in the other direction (and raising voltage to get the performance back). Of course the technology itself has certain limits. If you're already pushing the max voltage for the technology, it's hard to move to a lower FO4 without giving up performance.
I know for sure my designs are not making use of all that the technology can provide. The limitation comes from IP that I use. Let me explain...
One important consideration is that the industry is driven by miniaturisation. For consumer electronics, what companies care about is # of chips per wafer. However, the most miniaturised cells do not necessarily present the best trade-off. It certainly is area optimal, but not necessarily delay optimal. This relates to cell height (in number of tracks) and cell width (presence of dummies, local layout effects, etc). My point is that the industry is not necessarily adjusting for optimal FO4, but it is giving area a higher priority because of business-related reasons.
Aparna, this discussion is way beyond simplistic logical effort or off-chip loads.
Samuel Pagliarini , thanks for your comments. It's certainly true that design libraries these days may not be optimized for high-performance designs, just as the technology itself may not be, for the same reasons. It would seem that both of these "practical considerations" would tend to push designs towards higher FO4 design points.
Dear Warnock,
welcome,
This is a very interesting question in logic design concerning pipe lining. You speak about the optimum logic depth in a single stage of a pipeline constructed in high performance risc microprocessor. So, one has to assume that one is given a technology file defining the devices and the layers of the technology and its minimum dimension.Also, the operating voltage is fixed. In addition, the FO4 is given and the highest frequency is defined.
In order to design a pipe line one has to determine the overall delay time of the pipe line, the number of the stages in it and the operations carried out by every stage. That is one has to divide the operations on the different stages such that the time taken by each stage is equalized for the highest possible activity among the hardware.
This important topic is studied in details in the literature: http://people.duke.edu/~bcl15/teachdir/ece590_fall14/Presentation_Pritam.pdf
Best wishes
Yes, thanks for that nice description of the problem, for those unfamiliar with the subject. But, as you describe, it's possible to divide the pipeline up into many fine stages (ie the time taken by each stage is a relatively small multiple of the FO4 delay), which would let the processor run at a high frequency, albeit with all the drawbacks mentioned at the start of the discussion. Or, you could divide it more coarsely, with fewer stages, in which case the operating frequency is lower, but CPI would likely also be lower, and the design might be more efficient in other ways as well. So the basis of this discussion is the question of where the optimal solution might lie (ie optimal number of FO4 delays per pipeline stage), for a general, high-performance RISC processor?
OK, a little more for the discussion. Some previous studies have come up with some pretty small FO4 numbers as being optimal. For example, Hrishikesh et al (http://www.eecs.harvard.edu/~dbrooks/cs246/deep-pipes.pdf) would suggest about 8 FO4 as being optimal. However that work did not try to address power efficiency. For example, in their figure 7, going from an 18 FO4 design to a 8 FO4 design (including clock/latch overhead), improves performance by 35-40%. However, active power would presumably increase by 18/8 (frequency scaling) and maybe at least another 2-4x for the increase in the number of latches and other logic/design inefficiencies. If one assumes that chip frequency and performance scale perfectly with voltage (optimistic), and power with the frequency time voltage squared, then, a 1.4x performance advantage could be traded off for a 1.4**-3 = 0.36x power scaling, or about a 2.7x reduction in power, at constant performance. Even this would not appear to be enough to compensate for the increased power of the design (say 4.5x-9x). In general, the performance curves in this work are pretty flat, suggesting an optimal point beyond the limits of their study, ie >18 FO4. Also, the fact that wires have not scaled perfectly since that time, would also push towards a higher FO4. Would be interested to hear other folks' opinions on this matter.
OK, not much action here... let me add a few more of my own comments, at the risk of injecting my own bias. First, another reference, from the Brian Curran et al POWER6 paper: Article Power-constrained high-frequency circuits for the IBM POWER6...
In their figure 2, they show that, for this design and technology, the optimum performance is about at 13FO4. Now, this analysis was done without a power constraint, so similar to the discussion above, it seems unlikely that the performance gain going from 18FO4 to 13FO4 (about 11%) would be enough to offset the power increase. Or, to put it another way, the 18FO4 design, designed for, and operating at a higher supply voltage, would likely deliver higher performance at the same power as the 13FO4 design (operating at a lower voltage to keep the power in check). It seems likely then that the optimal point is somewhere above 20 FO4, at least. But this raises an interesting practical question. If one were to continue increasing the FO4, lowering the frequency and raising the voltage, moving towards ever higher performance design points (subject to the power constraint), what happens if the power constraint is "weak" enough such that the design reaches the technology's maximum voltage before the optimal FO4 is reached? In this case, the optimal FO4, from a practical point of view, would be that which yields a design which just meets its power constraint while running at the maximal allowed voltage. The corollary would be that, a downward adjustment in Vmax would tend to push the design point down towards a lower FO4, unless the power constraint is also adjusted accordingly (perhaps to allow more parallelism/more cores). Or, one could say that in this situation a stronger power constraint would tend to push the design towards a higher FO4 design point (up until the point where the design reaches the "true" optimum). Further comments anyone?
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