I dedicate this question to my students from Faculty of Computer Systems and Technologies of TU Sofia (groups 44, 45, 46 and 47)...
A few months ago, I asked a similar question (surprisingly, still unanswered?) about the bizarre circuit of DRAM sense amplifier:
https://www.researchgate.net/post/What_is_the_basic_idea_behind_the_DRAM_sense_amplifier_Can_we_think_of_it_as_of_a_negative_load
There I told how, in the past, I could not understand how a DRAM cell can be refreshed by simply reading. I was able to imagine how this could be done by reading and next writing... but I was not able to imagine how it could be done only by reading...
At the beginning of yesterday's lecture on DRAM, to motivate my students to reveal this brilliant circuit idea themselves, I told them my story. Then, with the help of analogous situations from our daily life (some of them a little fictitious:), we managed to explain it in a simple and spectacular way...
So we already know what the main function of the sense amplifier is in a DRAM - to refresh the contents of the cells. But what is its function in an SRAM where there is no need for refreshment, but only for simple reading? Why do we use there such an odd 2-terminal amplifier?
The conventional amplifier is a 4-terminal (2-port) device - it has an input (port) where to apply the input voltage and an output (port) from where to take the output voltage. Can not we read (and amplify) the contents of the cells with its help? What is the need for such a weird amplifier having only two terminals?
This morning, the answer to this old question suddenly emerged in my mind. I clearly imagined how to present it to my students to understand the need for such a unusual circuit solution in SRAM.
I will spend some time at the beginning of the next lecture on Thursday to unveil this need with the same success as we did in the lecture on DRAM.
I hope this time you will not remain impartial and will support us...
The transistors in the SRAM cell are functioning as amplifiers; it is the internal positive feedback that creates the bistable operation that is used to store information. However, the sizes of these transistors are kept as small as possible so that more of them can be fit into a given amount of area, and to keep leakage currents as small as possible.
When a read operation occurs, the outputs of the four internal transistors are connected to the bit lines by the word-select transistors. The weak internal transistors need to drive the bit lines low/high through the select transistors, which means that the available signal is somewhat attenuated, both by the voltage offsets introduced by the select transisors and by the relatively high capacitance of the bit lines. The resulting differential signal doesn't look at all like a "normal" logic signal.
It is the purpose of the sense amplifiers on each pair of bit lines to turn that weak differential signal into a normal logic signal that can then be fed to additional data multiplexers and/or I/O pin drivers.
that's why these exotic circuitary..
Dear Vinoth,
Thanks for the excellent answer... But still how can I justify the need for such an exotic circuit (rather a latch than an amplifier) to my students at the lecture on Thursday? Can not we use the well-known 2-port amplifier?
The W/L ratio of the MOSFET shows that it will behave in different sitiuations,the latch based sense amplifier consists of 6 transistors out of these 4 will be sized,the latch within sense amplifier consists of pair of cross coupled inverters which are identically sized both p are identical and n too in addition to latch sense amplifier contains 1 pmos transistor for enabling and disabling power to latch, NMOS transistor N1 which is used as a current source for the sense amplifier. The different components of the sense amplifier will each have different effects on the overall design. Because of this, the amplifier will be designed in three separate parts. The sense amplifier will have the inverters for the latch sized first, followed by the current source transistor and the enable transistor.
A professional explanation... but I have to explain this to students in a simpler way... to show them a simple reason for using such a unusual amplifier...
By the way, what is the role of the current source in the sense amplifier? Can you provide a circuit diagram of this kind of sense amplifier?
Thanks for the circuit diagram... And you consider N1 as a current source?
Hi Dr. Cyril Mechkov,
I have a simpler answer.
Bit cells of SRAM are made very small to reduce the cost. Thus, turning bit-lines to logic 0 or 1 using small cells require much longer time.
To solve these issues both bit-lines are precharged to Vdd (logic 1). A single cell is electrically connected to bit-lines for a small time to make a small difference in voltages. Later, the sense amplifier senses that difference and convert that small difference to logic 1 and logic 0.
For more details please read my paper-
https://www.researchgate.net/publication/275061790_SRAM_precharge_system_for_reducing_write_power
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