The design is divided into module, its consist of three module, these module are run on FPGA based on time slot, t0 module0, t2 module1 and t3 module3, again t4 module0 repeat it. How will performance, partial reconfiguration is solution for this, Or any other method in FPGA.
If the modules are cascaded, then you can build from them a pipeline where the output of the first module is delivered to the following module in the second module where it starts operating on the signal until finished. Then it delivers its output to its trailing stage until the whole processing is finished. The cycle will have a number of phases equals the number of the modules. The phases may be equal with a duration equal to longest processing time of any module.
It can so that asynchronous hand shake transmission between the different modules can be utilized. When the first stage is finished it sends a request to send to the following sage when it is ready it reacts to the request with ready to receive. After receiving the input it starts operation till it is finished and the procedure repeats again with asynchronous transmission between the second stage and the following third stage and so on till the the last module finished.
There is two methods of timing the modules the synchronous mode and the a synchronous mode. In the synchronous mode you use a a master clock. While in the asynchronous mode different clocks can be used for every module.
The issue of the timing is an important topic and one has to refer to its specialized literature.
Best wishes
check this simple paper , it might help
https://pdfs.semanticscholar.org/3983/df804d2f13b57b6db2df94f545038b33d867.pdf
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