I have a set of impedance spectroscopy data that I am analyzing. I see the phase angle - among other parameters changing systematically with annealing temperature and bias voltage. Example: the width of the phase angle peak shifts towards higher frequencies. I have not found a paper explaining the physical meaning of this observation especially for dielectric/oxide thin films.
I suspect that a change in the bias voltage from zero would change the distribution of interface states at the oxide-semiconductor interfaces (for MOS structures) and therefore a shift in the capacitance and hence phase angle from impedance measurements. Is this understanding correct?
I don't have a full answer for your interesting question. However, from past but extensive experience with MOS CV, I have found that results are often confused by incomplete electrical models. In particular, for a MOSCAP, the series resistance presented by the wafer is a big issue. Also, unless particular care is take, the backside contact may be non-linear and thus really confuse measurements. With proper care, you may be able to get at the capture/emission time constants of the interface states themselves, but only after effects such as these are properly accounted for.
A "peak" in the phase angle corresponds to a time constant of the system. The associated process becomes faster, the associated "peak" shifts to higher frequencies. I am not familiar with your experiment but my feeling is that increasing the bias makes the resistivity decreasing because of the increment of charge carriers, which leads to the observed behaviour.
The change in the phase angle is such that it decreases towards zero in the low frequency region but the high frequency regime stays close to 90 deg and The spectra shifts to the right with increase in bias voltage. The same trend is observed for MOS structures annealed at increasing temperatures
- Badges
- Science topic
- Similar topics
- Physical Sciences
- Physical Phenomena
- Luminescence