Dear Hossam,

From the industrial point of view, I think there is no real difference between VHDL and Verilog HDL. They are often sold together, and they offer the same possibilities and have nearly the same amount of existing open source codes. I advise you to use the language that most people around you use, or to use the language you understand more easily.

Best regards

Thanks a lot

I would like that you follow the link: https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/

You will get a comparison between the two languages.

The two languages are used equally well in academia and industry environment. Every language is supported by their FPGA chip makers.

Best wishes

Thanks a lot Prof. Zekry for your feedback.

Aparna Sathya Murthy Francois Auger I'm totally agree about the flexibility of choose between both of them, but could you be rejected to join a company just because you are not familiar of using Verilog but expert in VHDL?

Verilog

Hossam O. Ahmed , I can image a theoretical situation, where a specific, rather small, team is "fixed" to the one of the HDLs, all projects are made in this one and further developing has to be stuck with it. So this one would be obligatory.

But in the real world it looks rather that more important is to be skilled HDL designer in language of choice.

Notice that even at the project level you can use both, Verilog and VHDL sources, seamlessly. Being first in the team, who is skilled in the other HDL would be more often an advantage than a weakness (as you can use other half of open source resources).

i think vhdl

As already commented, there are no substantial differences between the 2 languages. What it matters is the Hardware-design mindset, then it is just a matter of different syntax.

I have been using both of them in "industrial" environment and I did not noticed any difference/preference in they use of one over the other.

In general, but I guess this is getting less and less apparent, in European Countries and Industries VHDL has been the go-to language of choice, while in America Verilog was more prominent. However, it heavily depends on the coding rules that are adopted by the company (e.g I currently work in a company where new design, with few exceptions, are SystemVerilog based, while legacy ones were VHDL).

In order to facilitate the integration with Test-Benches written in SV, I have noticed now that sometimes there is the tendency of preferring Verilog as design language, but as I said it depends on the company rules.

In my opinion VHDL has a stricter syntax, while in Verilog it is easier to use "tricks" (this is my opinion, so please do not take it as a general rule/fact). So, in my experience, VHDL is somehow better when it is time to learn how to design with hardware in mind (i.e. to understand what is an efficient hardware description with respect to what it is not or poorly synthesizable). In that sens, having a stricter syntax facilitate (in my opinion) to assimilate what is good practice.

Having said that, when it comes to Netlists and interface towards Back-End, Verilog it is the only language of choice!

Bottom line, both languages are perfectly equivalent and when the mindset is there, it is easy to switch between the two.

I apologize for this long answer, but I hope it brought up some points that you might find interesting

Historically, VHDL has been the choice for Europe/FPGA markets while verilog has been the choice for US/ASIC markets. In terms of capability of expressing design intent, both languages are equally powerful. There is no piece of hardware that you can only describe using one or the other.

In terms of tool support, all major vendors support both for many years now. You can also mix and match and that is well supported too. (this was not the case many years ago)

Basically, VHDL is somewhat better defined than Verilog. But when you look somewhat closer, you'll find blocks written in Verilog, wrapped for VHDL compatibility. (Not sure whether wrapping is also done the opposite way - I'm a European, thus somewhat addicted to VHDL :) )

It matters where you will be doing the coding: Europe and America East Coast is VHDL, Asia and America West Coast is Verilog. Ottawa/Kanata is also mostly Verilog. So, the one that your customer prefers, is the best language ... lol

However, now, with System Verilog, I have seen the big companies converging towards Verilog (Xilinx Vivado as an example, but still supports VHDL)

The VHDL wrappers are done so that you can use the Verilog modules in a mixed language environment without having to rewrite them in VHDL. It happens the opposite way when one tries to include VHDL written modules in an Verilog based top-level design.

Cheers,

Petru

Both the languages are for the same purpose but it depends upon the designer, how perfect he is in writing code. Personally I am more comfortable in Verilog instead of VHDL.

Verilog HDL is more user friendly language compare to VHDL. In current state of art industries adopting system verilog for their industrial needs.

Baseline is: VHDL and Verilog are equivalent, commonly supported and can be mixed, wrapped, whatever. And yes - the crucial skill is hardware design, not the language. So there is free choice and no visible superiority.

But there are secondary issues deriving from fact that all (?) ASIC/FPGA tools are made in USA, and USA loves Verilog.

#1 Some design examples for IP cores in VHDL are worse than in Verilog (e.g. Xilinx).

#2 Some IP modules generated in VHDL can be different/mistaken (all vendors).

#3 Some specs for advanced synthesis techniques for VHDL are mistaken (e.g. Synopsys for Microsemi).

#4 Some VHDL simulation models for IP cores, involving mixed-signal techniques (PCIe, transceivers etc) do not exist or are mistaken (all vendors)

#5 Same for Bus Functional Models and other stuff for simulation.

#6 IP modules or BFMs can be generated in both VHDL and Verilog, however the deep-low-level parts are usually only in Verilog. If you choose VHDL then you get mixed language design. No problem for synthesis, no problem technically, but when it comes to simulation you may discover that your version of simulator (e.g. ModelSim for Intel/Altera) does not handle mixed language designs, so you are forced to purchase "a-bit- more-expensive" version (e.g. ModelSim PRO).

Conclusion is - you can live with VHDL if you like it, or need it, or make money on it (e.g. in USA, guys who can do in VHDL are perceived as valuable experts!). But if you don't know or don't care, you'd better go for Verilog.

In my opinion verilog is more efficient compared to VHDL. Moreover, industry is preferring verilog over VHDL. Older VHDL based systems are replaced by verilog.

Please, I am interested in learning how to use Verilog on FPGA. If you know of any resources like a tutorial on Verilog and design with the FPGA board. please, do forward any available resources via my email: [email protected]. Thank you in anticipation.

Iyapo Kamoru.o.