I am designing a circuit require 128 bit vector input with Cadence Virtuoso tool at gpdk90nm technology. Can I provide input as verilog Test bench ?
Do you want to simulate transistor-level (electrical) design and provide stimuli generated by Verilog module? If so, you can have two options. Both have prons and cons.
1) Use Verilog-A module (analog behavioral description - which might be anything) to generate the stimuli. The stimuli are analog signals but created in a procedural way. The advantage is that Verilog-A is simulated by Spectre so you can use ordinary analog ADE setup. But you have to learn how to write Verilog-A model.
2) Use plain digital Verilog which I guess you know already and simulate your mixed-mode (analog-digital) project using mixed-mode simulator which is available in standard Cadence distribution and is called AMS. But using AMS simulator requires some additional work. You have to create config cellview for the project and change some parameters of the connect rules so the "0" and "1" generated by the digital part of your project will be converted to required voltage levels.
Wish you success!
Thanks sir, I have got alternate way more or less it option A ( verilog -A). I have got busset8 in BMSLIB library. Where we can define 8 bit static inout value.
We can create larger size bus by embedding multiple busset8 cell in a symbol like busset128.
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