Hello Sir,

In principle, this is possible. In the past, I dont know how long ago, I have seen an article about full-adder based structures (adders, multipliers) using 4-level logic, and this seemed to work.

Note, however, that this is against the trend microelectronics is following: The main process is (deep submicron) CMOS, and then there are 2 problems of multi-valued logic, being:

1. The noise margin - The transistor Vt tolerances are large, and the deeper submicron, the more tolerance there is. This works against using multi-treshold.

2. The power dissipation. - CMOS is essentially dissipation-free in the '0' state and the '1' state, not sure how you can preserve this in 4-state logic. Note this is very important, as everything is about power dissipation these days.

Regards,

Henri.

Thanks a lot Henri and Chung

MVL I do not know but in Ternary Logic yes.

Dear Ingole Sir,

Please give some suggestions or techniques sir..!

good question