Hello Jiang Cao

I Have two questions about "Operation and Design of van der Waals Tunnel

Transistors: A 3-D Quantum Transport Study". Please help me in this matter.

1-  when low dimensional materials form an interface with standard semiconductor oxides like SiO2, they have interface traps. Has this been considered in the simulations? If not. why?

2- Why is it not a standard double gate MOS structure? What is the role of displaced gates? Has this been validated?

Thank you for your attention.