In the design of power converter ICs, sometimes the power switches are not given by the PDK. That means we have to design the power transistors as the switches (NMOS and PMOS).
Since the power loss causes by conduction loss and switching loss, the power efficiency of the converter is decided by a very well trade-off between these losses. The conduction loss depends on the Ron of the switch, that means larger switch (with larger Width of the transistor), the lower conduction loss. In the mean time, the switching loss increases since the parasitic capacitor of the power switch increase.
So I would like to know the method of sizing the power switches in the converter for maximizing the power efficiency. Any ideas or recommendations/reference papers from you are highly appreciated. Thank you so much.
For any MOS switch the losses can be expressed by this relation
ploss= Pstat + pdyn= Ion^2 Ron Ton/T +CVdd^2/T where T=1/f with f is the switching frequency. Ion= un cox w( ,Vgs-Vtn)^2/2L, Vgs=Vdd , Ton = T/2 for square wave operation with a duty ratio =0.5, C= Cgs= cox wL, Ron is also a function of w. So, can get an optimum w as the on losses decreases with increasing w while the dynamic losses increases. Therefore there will be an optimum value which give a minimum of the power losses. L is taking as a minimum feature size.
Best wishes
In principle, sizing is simple - requiring the desired switching frequency, operating voltage and current as rhe main parameters. For these you'll get curves for switching and conduction losses over different MOSFET geometries. The optimum is the minimum of the addition of the curves.
Btw: the high-side switches today are NMOS as well - requiring level shifters or isolation paired with a "fkying supply".
Thanks for your comments.
Could you also provide some guidance in more detail view about this such as test-bench or references. Really appreciate your help.
Hello,
eventually the following paper may help you:
https://www.infineon.com/dgdl/Infineon-WhitePaper_PowerLoss_and_Optimized_MOSFET_Selection_in_BLDC_Motor_Inverter_Designs-ATI-v01_00-EN.pdf?fileId=5546d46253f6505701549f2799aa4b53
If you need more: why not use google? "losses mosfet power stage half-bridge" is a nice search string :)
Regards
Thanks Dr. .Dreher for your nice recommendation. However, it is still not exact my point since I want to sizing the power switches in the Cadence environment for low voltage, low power applications. What I want to know is the methodologies for sizing power switches as well as how to evaluate these losses. There are many resources and guidance on the internet and paper about the losses in switching dc-dc converter; however, it is very common and I still have not reached to the solution with a clear procedure in sizing power switches for high power efficiency.
Also, thank so much for your comments
Well , if you mean realistic (Cadence ) sizing metrics then DFM files are needed .
It is basic that the sizing of a MOSFET is proportional to Ids (or drive currents)
https://www.globalfoundries.com/sites/default/files/product-briefs/pb-180bcdlite.pdf
For any MOS switch the losses can be expressed by this relation
ploss= Pstat + pdyn= Ion^2 Ron Ton/T +CVdd^2/T where T=1/f with f is the switching frequency. Ion= un cox w( ,Vgs-Vtn)^2/2L, Vgs=Vdd , Ton = T/2 for square wave operation with a duty ratio =0.5, C= Cgs= cox wL, Ron is also a function of w. So, can get an optimum w as the on losses decreases with increasing w while the dynamic losses increases. Therefore there will be an optimum value which give a minimum of the power losses. L is taking as a minimum feature size.
Best wishes
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