There are surges in the current of PMOS and NMOS during dead-time (as in the attached figure). I have several questions:
- First, is it serious or bad in my design? And if it is not good, how to solve it?
- Second, in the design of buck, boost, buck-boost converters, current sensing technique is used for current-mode control and over current protection features. Therefore, the high precise sensing current of PMOS switch is needed and important. However, due to the surge current in the deadtime from the PMOS current waveform, the sensing current is also bad (of course in the deadtime) since the sensing current is a scaled version of PMOS current. Please recommend some instructions.
Thank you very much!
Dear Van Ha,
Looks like you're only simulating your system...
Set it up and do measurements in real life. Then, if your problem physically does exist, try to solve it using proper gate drivers with reasonable dead times.
You may be hunting a simulation phantom not existing in real life.
Cheers - Martin
Dear Dr. Martin Schulz,
Thank you very much for your guidance. Actually, I am designing an IC on Cadence pplatform so a proper design with high accuracy is a must. As you pointed out, the problem relates to the deadtime which shoud be carefully designed. I have improved it further and it is better when I use a smaller deadtime. With smaller deadtime, the surges in NMos switch was reduced but surges in Pmos switch does still exists at time when NMOS is turned off and Pmos is also off. Perhaps this surge comes from reversed recovery current from the body diode inside Nmos switch that affects on drain current of high side Pmos switch. I am still wondering:
1. Could surges in PMOS swill reduce further by improving gate driver, especially with a reasonable deadtime?
2. Since in my design, special power devices for Power switches are not available from PDK. Therefore, I have to use normal MOS device for designing Power switched. This means the body diode inside the NMOS switch is just the parasitic diode and its response is not high enough when it is turned on and off (when both Pmos switch and Nmos are off in the deadtime, body diode of Nmos switch must conduct the inductor current for a while). If this causes high current surges in the deadtime, are there any solution for improving the issue?
3. Because PMOS switch current will be sensed for functioning of current-mode control as well as over-current protection. Now there are surges in PMOS switch current, so the sensing current also has the surge. Are there any techniques to sense the current but eliminating the surge to get the correct PMOS switch information?
Thank you so much for your great support.
Sincerely,
Van Ha
Hello Mr. Nguyen,
It was a while since you posted this so I don't know it you are still interested, but here are some comments:
Without schematic and zoomed-in pics of transients and desription of models used one can't say much for sure. One thing you could check is if reverse recovery time of drain-source diode is the cause. If so then perhaps the energy is negligible in the pulses - what is the pulse length? And in the pic I cant even see if dead time actually is big enough or not, you have to zoom in to see, and this parameter can often be selected for driver IC. And look at all parts of model that might cause capacitances.
I don't think filtering out such pulses is a common issue with a known recommended solution as you seem to imply. I mean, there are situations in SMPSes, like when leading-edge blanking is used in current mode PWM controllers, where there are known glitches that have to filtered out to be able to regulate well. But I can't think of any other such situations. On the other hand in an SMPS one or two small RC filters on sensitive signals might be of use.
I agree measuring in real life is generally a good idea but has its own set of problems. Note! Ground oscilloscope at point close to measurement. If you see transients then first try moving probe tip to its own GND probe (so that it is short-circuited). If transients remain then this exercise proves the transients are false - which they often are in such situations (coupled directly to probe). If so then you will have to improve probe which is a whole different chapter. You could start by minimizing probe lengths and loops and avoid ground loops.
Good luck!
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