Dear Faiq Khalid,
I suggest you to see links, attached files and publications in topics.
- Integrated Circuit and System Design. Power and Timing Modeling, ...
https://books.google.dz/books?isbn=3540390944
- Integrated Circuit Design. Power and Timing Modeling, Optimization ...
https://books.google.dz/books?isbn=354045716X
Best regards
Article Performance optimization of digital circuits
Article Power - Performance Optimization for Digital Circuits
Article Modeling and simulation of the IR-Drop phenomenon in integra...
Conference Paper Circuit performance optimization for local intra-die process...
I would suggest looking into ASIC designs (they are cell based) . The way these work is gate has characterized devices (say in terms of switching frequency ) . A gate with known metrics of such device (say 2 devices or 4 ) then they are just summing (roughly ). .
Majority of low-power VLSI design research works discuss variety of power and delay models by making various assumptions such as gate-depth, and device parameters, transistor width, channel length, gate capacitance etc. In general, both power and delay are modeled as a function of supply and threshold voltages. Majority of the delay models rely on the power law model. while for power it is based on the leakage power and dynamic power models. usually dynamic power is approximated as 1/2*f*C*VDD^2.
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