How to mathematicaly model Setup and Hold time of the NAND gate based D flip-flop

07 July 2017 1 3K Report

What is Setup and Hold time in NAND gate based D flip flop.

But there should be some generic way to model them, like timing differences of which transistor or gate is responsible for setup and hold time in D flip flop. To my understanding, in the NAND gate based D flip flop the setup time is equivalent to delay of one inverter and two NAND gates, and the hold time is equivalent to one inverter delay.

I just want to confirm that is it correct or not?

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