I have designed Wallace sign multiplier using reversible logic gates as well as using Irreversible gates(HA,FA,AND Gates ).I am getting power dissipation less in irreversible multiplier than reversible multiplier.According to theory reversible logic circuits one of the best way for power optimization.how?
Yes..cadence 180nm technology... for reversible multiplier i got 12.54mw and normal multiplier am getting 0.604mw
The reason of this is that you have designed a digital circuit which behaves as a reversible multiplier (i.e. you have the same input-output functionality only). The designed circuit is not reversible in its own nature. It is built from irrevesible gates. The common CMOS gates do not exhibit the property of energy conservation (i.e. they are not energy efficient because they consume the energy - static as well as dynamic).
According to me, For reversible circuits, There is no matured tool in the market to calculate the power(it is in research level). But you can calculate the other parameters like quantum cost, garbage input and output , logic depth using Revkit tool. after verifying the functionality using xilinx or altera
i am also facing the problem when trying to prove the concept of reversible circuits consume lower power than the irreversible design.
Yes we can calculate the other parameters like quantum cost, garbage output, Ancilla inputs , logic depth . But these parameters can be used to prove within any of the reversible circuits. If i understand correctly, we can not compare reversible and irreversible circuits using these parameters. Please correct me if i am wrong.
According to my knowledge based on work done so for, For a target circuit ( example Half adder, Full adder and the like) reversible circuits always have more transistors leading to more switching resulting higher power consumption than the irreversible circuit .
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