Hi all,
As we all know, the threshold voltage reduction is one of the key techniques being used in low power mixed mode IC designs. There've been different techniques outlined in different sources, apart from that I was wondering whether the MOS re-sizing can be used in the same way to realize the requirement. In other words can we use so called short and narrow channel effects in away to facilitate our requirement, while preserving functionality in threshold and sub-threshold regions ? (I'm aware that it could affect the mismatch performance of the device). And do we have a mathematical representation of threshold voltage roll-off ?
I have tried transistors of many extremes in size and aspect ratio (W/L) without noticing any change in Vt. It is just the nature of a MOS transistor that Vt is dependent on doping. A wider channel will get you only more current (or more leakage) for a given gate voltage. A shorter channel will only get you more leakage and finally breakdown. The channel length affects source-drain breakdown but not Vt.
There is a very important role for transistor sizing in certain low power design techniques. If you are designing for subthreshold operation, you will find that the ratio of PFET to NFET current capacity may be much different. If you have accurate models you can figure this out with Spice. It is not obvious that the average BSIM model produced by an ordinary process vendor is really accurate for very low voltages.
Dear Sir,
- The transistor treshold is regulated by the channel implant. By using doping techniques, a channel implant is put in place, and by varying , it is possible to get the desired treshold voltage.
- The treshold itself is a trade-off between leakage current and speed, required Vcc voltage.
-> Lower treshold means higher leakage, but also better speed, possibility to work with lower Vdd.
-> Higher treshold means lower leakage, but slower gates, requirement for higher Vdd.
Cheers,
Henri.
Thanks for both replies. One thing to note, in BSIM3 and 3v3 manuals it's mentioned that the reduction in channel length causes the threshold voltage roll-off but in turn increases the leakage current as both of you noted. Well this leakage power and speed trade-off is an obvious thing. No need to summarize that.
For an instance, in ST 130 nm transistor models, the threshold voltage dependency over channel length and width has been outlined (cannot share it though). What I wanted to know is whether this phenomena being put into practice ? Or in anycase this is used as a technique ?
I suggest you look at the following:
Section 3.2.2 in http://perso.uclouvain.be/david.bol/papers/2008/Bol-PhD08.pdf - also much other useful information in this book length free document. Basic contention of 3.2.2 is that Vt has no effect on Emin as long as you operate in subthreshold.
Also see http://www.soiconsortium.org/pdf/Ultra-Low-Power_Roadmap.pdf page 3, Reducing Emin. You want low Vt variability (use of any geometry techniques will increase variability), and of course low leakage.
The following book is very good, but somewhat expensive: http://www.amazon.com/Ultra-Low-Power-Integrated-Circuit-Design/dp/1441999728/
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