To build the most elementary storage cell (latch, SRAM cell) we take a non-inverting amplifier (Fig. 1) and simply connect its output to the input (Fig. 2). For some reasons, we implement this configuration by two cascaded inverting stages (Fig. 3):
https://www.researchgate.net/post/How_do_we_present_in_an_attractive_way_the_basic_idea_behind_the_most_elementary_memory_cell
https://www.researchgate.net/post/Is_the_elementary_SRAM_cell_an_RS_latch
In its simplest form, this cell is implemented by two transistors (SRAM - Fig. 4) or logic gates (RS latch).
So, naturally, the question arises, "Why do we need two transistors? Can not we realize a cell with only one transistor with positive feedback?" If possible, we would reduce the size of SRAM twice... and it would look like DRAM!
In fact, this issue comes down to the more general question, "Can we apply positive feedback to a single transistor?"... and even to the more primary question, "Can we make a non-inverting amplifier with a single transistor?"
It is interesting that the answer to the dual question, "Can we apply negative feedback to a single transistor?", is positive. Here are some examples:
- "Active diode" - a transistor whose base is connected to the collector (parallel negative feedback)
- "Current-stabilizing diode" - a FET with a current-sensing resistor in the source and gate connected to the other end of the resistor (serial negative feedback)
Then, once we can apply negative feedback to a single transistor, why can not we apply positive feedback?
In the beginning, I will clarify that this discussion is dedicated only to this not physical but "purely circuit" way of memorizing - by applying a positive feedback to an amplifying element.
Supprisingly, it is still the same - from the time of Eccles and Jordan (1918) until now...
Aparna, it seems an additional pass transistor should be added to ensure the access to the memory cell...
Aparna, there is nothing simpler than a pass transistor - this is just a serial switch...
Aparna, what is wrong with "floating" circuits? That you have no mainstay on which to "step":)?
Aparna, I wonder if it is possible to make a circuit without any ground...
Dear Cyril,
welcome!
perhaps the best thing in your questions is that one is motivated to rethink the subjects again and revisit them after they got well established. I my self benefited from these questions.
I gained two main things:
perhaps i can concept better working devices
and clear understanding such that i can describe the objects in a more clear way.
This is your right to acknowledge your effort.
Sometimes the discussions get long and tedious to follow as they are sometimes diversified to many related topics. This may make the folloing of the topic very tedious.
Therefore to be more useful i would propose that you filter out the answers and write an essay at the end containing the most descriptive answers.
Best wishes
Oh, Abdelhalim ... if people were so humane, helpful and gracious as you, the world would be wonderful!
If we were a little better and did not just think about what we have done... but we appreciated or just noticed what others have done... the discussions would have an incredible atmosphere.
Thank you very much for accurate assessment, thorough analysis and wishes about the organization of questions. Actually, a few years ago, I started to collect my contributions in the form of such "essays" (datasets)... and I am still going to restore this tradition in my profile...
Perhaps the RG software is trying to do something like this by putting the most popular posts at the beginning of each discussion. But really your idea of summarizing the most descriptive comments at the end of the discussion is interesting...
Best regards,
Cyril
OK, let's return to the topic...
As H&H say on page 119 of their bestseller:
"First, with the source grounded, a FET is turned on (brought into conduction) by bringing the gate voltage "toward" the active drain supply voltage. This is true for all types of FETs, as well as the bipolar transistors. For example, an n-channel JFET (which is automatically depletion-mode) uses a positive drain supply, as do all n-type devices. Thus a positive-going gate voltage tends to turn on the JFET."
... it turns out that we cannot make a non-inverting amplifying transistor stage... so we cannot apply a positive feedback to it... and we cannot make an SRAM cell with only one transistor...
But looking at the characteristics of various FETs in the picture above, my attention was attracted by the PMOS enhancement FET. It seemed to me that it was possible for us to solve the problem... and my confidence became stronger after I found this practical material:
http://learningaboutelectronics.com/Articles/P-channel-MOSFET-switch-circuit.php
My idea is to insert a resistor between the drain and ground (like in the case of the emitter degeneration)... and in this way to introduce a positive feedback in the stage. Thus the voltage drop across the drain resistor will act as a negative input voltage... that will bring into conduction the FET... its drain current will increase... that will increase more the voltage drop across the resistor (the input voltage)... and so on... As a result, I think, the FET will be fully turned on... and will stay (memorize) in this state... and the buzzer in the picture will sound continuously:)
At the same time, I feel a little hesitant because, as far as I know, a FET is controlled by the voltage VGS... and the load is connected in the drain... From this perspective, it turned out the PMOS in the picture is controlled by the complement of VGS to the positive supply voltage... and the circuit acts as a source follower?
What is true then?
Dear Cyril,
welcome
A single transistor circuit can has only one natural stable state which is the transistor off state. The transistor is a fully controlled device in the sense if one remove the stimuli it returns to its original state. In an inverter configuration is when VGS=0. Then it remains that you want to affect and hold the on conducting state. This can be accomplished by holding VGS= VGSon. The question is how this accomplished? You need an other transistor with the collector of the other transistor connected to the base of the first transistor and vice verse. For example, two transistors one p mos and one nmos connected like that form positive feed back loop and their composite characteristics I-V curve has an S-shaped curve with negative resistance like that of the thyristor.
It remains also to add an addressing transistor to complete the SRAM cell.
One transistor SRAM can be theoretically implemented by a capacitor and an addressing transistor with the conditions of:
- the leakage in the capacitor is zero
- the leakage in the transistor is zero
That is the SRAM could be a special case of the DRAM.Here one can preserve the capacitor in two stable and distinct static charge states.
Best wishes
Yes, Abdelhalim... but why there is a need of two transistors? Can not it be just one?
OK, let's consider another suggestion...
Looking at basic 1-transistor voltage amplifying stages, we can note that one of them - the common base/gate stage is non-inverting. Then it seems we should be able to apply a positive feedback by connecting its output (collector/drain) to its input (emitter/source) through some "shifting" element (e.g., a Zener diode).
If, for some reason, the emitter/source voltage slightly increases, this will make the transistor vigorously increase its collector/drain voltage... and, through the positive feedback element, this will increase more the emitter/source voltage... and so on...
And v.v., if the emitter/source voltage slightly decreases, the collector/drain voltage will vigorously decrease... and this will decrease more the emitter/source voltage...
Will then the common base/gate stage begin memorizing? I know it will not... but we need to understand why...
A simple argument in favor of this "no" is that if that was possible, in 1934, the young Otto Schmith would made his "thermionic trigger" with only one tube...
Dear Cyril,
Assume you have such amplifier with one transistor say NMOSFET whose drain is connected to VDD through a pull up resistor and also its drain is connected to its source by a feed element say a zener diode with VZ smaller than VDD. The gate is kept at VDD for controlling the transistor.
The input is through the source.
If we want to write logic one we apply VDD to the source, the transistor VGS=0 and the transistor gets off. and the the drain becomes at VDD , the one is written at the drain of the transistor. If we remove the bit line source and make it open nothing will happen since the transistor is already off.
So, the logic one could be written and sustained.
Now we come to the logic zero we want to wright logic zero by applying zero voltage on the source, since VGS= VDD, then the transistor gets on and the drain potential gets low and the zero is written at the drain node.
Now let us test if the circuit will keep the drain mode at the low state when we open the source as we did with logic one operation. That is we make IS=0, and also ID will be zero and the drain pulls up to VDD. This means that the circuit can no sustain the on state of the transistor with partition procedural.
And this what i said in my previous post that the off sate is one natural state in a single transistor circuit while the one state must be forced or imposed as the transistor is a fully controlled device.
However there is a mode of operation where one can make the default of the circuit is the zero by operating write input source at only two states the zero and VDD while making the gate high when we want to write or read the bits other wise its gate is low.
Let us verify the operation of this mode:
write one , VS=VDD, VG=VDD, then VGS=0 and the transistors is off and its drain will be high= VDD,
Then let VS=VG=0, VGS=0 and the transistor remains off keeping VD= VDD,
write zero,
VG=VDD, VS=0, VGS= VDD AND THE TRANSISTOR GETS ON AND VD=low
and so a zero is written.
Let us make VG= 0 and VS=0, THE TRANSISTOR WILL GET OFF AND THE ZERO IS NO LONGER SUSTAINED.
The only possibility to keep the transistor on is to keep the gate voltage high and the source voltage zero so long the content of the circuit is zero at the drain.
So, in conclusion accordion to these analysis, the single transistor cell alone is not working. Even here the circuit here has two elements not only one. Normally the area of the resistor in the chip is much larger than that of the transistor and still it is not working.
I think the best and natural information storage element is the capacitor!!!!!!!!!.
In case of static ram one has only to keep the charge constant during the bit storage time. The work in this direction will bring more benefits.
Best wishes
Dear Abdelhalim,
I admire your mind, which gives you the opportunity to do such in-depth analyzes of electronic circuits... To admit, sometimes I find it difficult to navigate in them... and I lose the thread of my thoughts... but maybe that is due to age:)
Yesterday, walking in the University park and thinking about the "common-base configuration with positive feedback", I suddenly realized (insight:) that, in 1934, the young Otto Schmitt invented just that configuration (see the transistor version in the attached picture)...
As here, Q1 can be thought as connected in a common-base configuration. Only, for some reason(?), Q1s collector is connected to its emitter not directly but through an emitter follower (Q2). The voltage divider R1-R2 obviously acts as a "shifting element".
It is interesting to see why he had used this additional emitter follower...
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