Considering any CMOS technology, I am eager to know what is the upper limitation of MOSCAP design. Also I want to know that MOSCAP is larger than conventional on chip capacitors or not. For instance how to compare 1pF MOSCAP and a 1pF on chip capacitor regarding die occupation. Totally avoiding passive elements in chips can save lots of area, so I am looking for methos for realizing larger capacitors with smaller die occupation.
Make as many fingers as possible and make the fingers as skinny as possible to take advantage of infringing capacitance.
ESR (Equivalent Series Resistance) is a limiting factor for capacitors. A large value capacitor (tantalum, electrolytic, etc) has a high ESR. It will not filter high frequencies. A ceramic capacitor has a low ESR. It will filter high frequencies.
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