Dear Raghu
I think it is not advisable to implement the analog frequency modulation digitally by the method you intend. Digital frequency modulation can be implemented digitally by controlling a numerically controlled oscillator to generate two frequencies in the binary FSK or 4 frequencies in 4-FSK or M frequencies in M FSK. You can implement the analog FM by directly controlling a voltage controlled oscillator. You can use a PLL to demodulate it. I do not know what are your objectives my answer based on concepts.
Best wishes
For 70 MHz carrier, ADC/DAC bandwidth should be 2 times more with 1-bit more of resolution of DAC than ADC.
Hi Raghu,
I never implemented anything like this, so the following is just speculation.
Usually, the center frequency has to be quite stable; therefore something like a quarz oscillator is needed, outside the FPGA. Instead of using an oscillator delivering a harmonic signal which is then digitized with high resolution, I would choose an oscillator with binary output. The harmonics are easily filtered out later on.
You did not specify the information which is to be transmitted, so I assume for the moment that it is an analog signal in the audio domain. What kind of ADC you use depends on the required quality; the usual ones provide 16 bit resolution, and a sample rate below 50 kHz.
You could vary the frequency of your output signal by shifting the phase of the oscillator clock, and the phase shifting can be accomplished by a variable delay. There is a programmable delay line, implemented in ECL technology:
https://www.onsemi.com/PowerSolutions/product.do?id=MC100EP195
If you would succeed in implementing something similar in an FPGA, this would solve your problem: You would need two delay lines, each with a delay range a bit larger than the period of the 70 Mhz clock, i. e. about 14.3 ns. While the clock signal travels through one line, the other is programmed and cleared. I would feed each line output into a positive edge detector and a negative edge detector; then the ORed signals of both positive edge detectors control the set input of an RS flipflop, and the ORed signals of both negative edge detectors control the reset input. The output of the flipflop provides the modulated carrier.
The rate of phase shifting should depend on the amplitude of the audio signal. The computed delay time is taken modulo the clock period. So, basically you could multiply each signed result of the ADC by a constant, incrementally sum up the products (MAC operation), and take only the lowest x bit of the result if your delay lines have x control inputs.
At the output of the FPGA, you don't need a DAC but a low pass filter.
That's the modulation. At present, I didn't even start thinking about demodulation.
I would propose to use Mary frequency shift keying to mimic the analog fm. This would be a possible solution. you sample and quantize analog modulating signal and convert it into digital format and then control the frequency of a numerical controlled oscillator to issue the frequencies corresponding to numeral values of the modulating signal. If your A/D conveter resolution is n-bits then you will have to generate 2^n different frequencies spaced from each other by a frequency deviation delta f. Such type of multi carrier generator is used in frequency hopping system.
Best wishes
Thank u all for your response...
I did PCM and FSK in digital then DAC then analog FM... Demodulation is performed in reverse chain...
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