Hi,

normally the etch rate of SiN by KOH is negligible, so it should not be etched away. How thick is your hard mask?

Have you stripped the native silicon dioxide before PECVD? If not you may lift off the SiN together with the oxide, although the etch rate of SiO2 is slow in KOH. 

Hello Naim,

First, the very nature of a mask means it shouldn't really need protecting.

As Antoine highlights, you have not provided the thickness of your SiNx hard mask. If it is relatively thin any defects are more likely to cause issues. I would also echo Antoine's suggestion of removing the native oxide with a BOE dip. However, I have also had lots of issues with using SiNx as a hard mask with KOH etchant.

The pressure and temperature can make quite a difference on the quality of the SiNx layer, consequently you'll find etch rates of SiNx in KOH vary in literature.

Some suggestions:

you could try a multi-layer SiNx deposition, this should reduce defects and improve the robustness during etching (lots of literature, most focus on improved insulating properties), simply reach the target thickness over multiple depositions;

you could try a multi-layer stack alternating between SiNx and SiO2;

you could simply use gold as a hard mask (in my opinion this will be the most reliable).

For my application I switched to ICP RIE to create my channels but I assume you desire the angled sidewalls.

Hope you reach a solution.

Jules

Hello Naim,

I concur with the comments placed by Antoine and Jules. I would first remove the native SiO2 with a 1% HF solution, rinse and dry and immediately start the deposition. Depending on the proces settings of your PECVD SiN deposition you will get more or less hydrogen in your film. If you have high concentrations hydrogen in the film (especially if you deposit below 300C) the SiN is likely to be attacked by the KOH. An alternative is use LPCVD SiN. This is furnace grown at low pressure, high temperature and will definitely withstand the KOH etch. General information on SiN and hydrogen content can be found in the semiconductor textbooks (e.g Sze, handbook of semiconductor technology). More detailed information can be found  in many articles in the journals (e.g. J. of vacuum technology, J. of Electrochem. Soc. and J. of plasma physics).

One more idea: what are your mask dimensions (width of the mask lines and width of the open space in between)? Could it be that the V-grooves completely underetch your SiN and that you lift them off because of that? It would be nice to know if you loose your mask also at places where there are no features (so where you basically just have a flat layer of SiN covering the silicon). If it remains there, the problem is liftoff (whether it is by oxide or silicon underetch). If it dissappears also there, the problem is the SiN layer quality or thickness.

Hello Everyone

Thank you a lot  for the suggestion. I am sorry for the late response. I solve  the problem by annealing the wafer before the wet etch. Due to the annealing, the SiN mask remain standstill after  wet etching. Although i still have some crack on the wafer but it may be overcome by reducing the annealing temperature. 

FYI: Hard mask thickness: 300nm

Thanks again

Just to add a brief note, when you deposit SiN on silicon, you have to expect a strong stress of the silicon substrate (LPCVD nitride is worse than more hydrogeneted nitrades in this case). Patterning of SiN and hence creation of steep dishomogeneities in the film directly deposited on silicon may give rise to strong localized stress at the cut edges and the evolition of very tiny dislocation precursors. When etching Si with KOH the strain caused by the nitride pattern within silicon will enhance the etch rate below the same nitride from the pattern edge... As a consequence, lift off may be procured and you obtain the results you initially faced.

Thermally treating the sample before etching possibly allows a partial release of the initial stress, by just promoting the growth of deeper dislocations and so called Hu-loops towards the silicon bulk. This may help avoiding nitride liftoff, but it turn to leave structural defects in silicon... that is the cracks you observed in your second trial.

The way to avoid both problems and the above tradeoff is GROWING (not depositing) a SiO2 interlayer between silicon and nitride, with a thickness 1/3 of the nitride thickness (not much less than that). If you should need to deposit oxide instead than growing it, you would need a post-oxide-deposition Thermal process in nitrogen at 850 degC or more to densify the layer before depositing the nitride.

This interlayer strongly reduce or even eliminate the stress propagation caused by nitride, and moreover oxide etch rate in KOH is really negligible. Also adhesion of nitride over oxide is very strong so you will not face liftoff of nitride from oxide.

A POSSIBLE SIMPLER WAY:

you coul use Si oxide alone as masking layer, provided that you can grow a sufficiently thick layer (at least some hundreds nm) or deposit it and high-T annealing the same before patterning

Hello Naim,

Currently, I'm working with SiN hard mask and also facing some problems with its adhesion to silicon. Could you please tell me what was annealing temperature and time?

Hi Anton Vorobiov , I used silica and SiN as hard mask. As I recall, thee annealing temperature is around 800C for 1 hour with the gradual ramping process. Also check Giuseppe Curro response.

Naim,

Nitride depositions from PECVD are generally SiNxHy; and annealing reduces the H content ending with a KOH resistant mask. I suggest to reduce the thickness of your mask and anneal to prevent cracks, or keep the same nitride thickness and reduce the temperature of your annealing. In the last option, the etching rate will be very slow.

Ariel